16-Channel, 16-/14-Bit,
Serial Input, Voltage-Output DAC
AD5360/AD5361
Rev. A
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FEATURES
16-channel DAC in 52-lead LQFP and 56-lead LFCSP
packages
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output spans available
Temperature monitoring function
Channel monitoring multiplexer
GPIO function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI-compatible serial interface
2.5 V to 5.5 V digital interface
Digital reset (
RESET
)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards
FUNCTIONAL BLOCK DIAGRAM
n
SERIAL
INTERFACE
8
6
n
n
8
8
14
n
n
n
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n
8
8
14
14
·
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n
n
n
n
n
n
n
n
SDI
SCLK
SDO
SYNC
BUSY
RESET
CLR
STATE
MACHINE
CONTROL
REGISTER
GPIO
REGISTER
GPIO
MON_OUT
MON_IN1
MON_IN0
PEC
TEMP_OUT
BIN/2SCOMP
TEMP
SENSOR
AD5360/
AD5361
A/B SELECT
REGISTER
n = 16 FOR AD5360
n = 14 FOR AD5361
·
A/B SELECT
REGISTER
X1 REGISTER
M REGISTER
C REGISTER
TO
MUX 2s
TO
MUX 2s
A/B
MUX
MUX
2
DAC 7
REGISTER
DAC 0
REGISTER
OFS1
REGISTER
DAC 0
REGISTER
OFS0
REGISTER
DAC 7
REGISTER
X2A REGISTER
X2B REGISTER
OFFSET
DAC 0
DAC 0
DAC 7
OFFSET
DAC 1
DAC 0
DAC 7
BUFFER
BUFFER
BUFFER
GROUP 0
GROUP 1
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
VOUT7
SIGGND0
SIGGND1
VREF1
n
n
n
n
n
n
n
X1 REGISTER
M REGISTER
C REGISTER
A/B
MUX
MUX
2
X2A REGISTER
X2B REGISTER
DV
CC
V
DD
V
SS
AGND DGND LDAC
n
n
n
n
n
n
n
n
X1 REGISTER
M REGISTER
C REGISTER
A/B
MUX
MUX
2
X2A REGISTER
X2B REGISTER
n
n
n
n
2
n
n
n
n
X1 REGISTER
M REGISTER
C REGISTER
A/B
MUX
MUX
2
X2A REGISTER
X2B REGISTER
MUX
VOUT0 TO
VOUT15
05761-007
Figure 1.
AD5360/AD5361
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
AC Characteristics ........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 14
Functional Description .................................................................. 15
DAC Architecture ....................................................................... 15
Channel Groups .......................................................................... 15
A
/B Registers Gain/Offset Adjustment ................................... 16
Offset DACs ................................................................................ 16
Output Amplifier ........................................................................ 17
Transfer Function ....................................................................... 17
Reference Selection .................................................................... 17
Calibration ................................................................................... 18
Reset Function ............................................................................ 19
Clear Function ............................................................................ 19
BUSY
and
LDAC
Functions...................................................... 19
BIN
/2SCOMP PIN ..................................................................... 19
Temperature Sensor ................................................................... 19
Monitor Function ....................................................................... 20
GPIO Pin ..................................................................................... 20
Power-Down Mode .................................................................... 20
Thermal Monitoring Function ................................................. 20
Toggle Mode ................................................................................ 20
Serial Interface ................................................................................ 21
SPI Write Mode .......................................................................... 21
SPI Readback Mode ................................................................... 22
Register Update Rates ................................................................ 22
Packet Error Checking ............................................................... 22
Channel Addressing and Special Modes ................................. 23
Special Function Mode .............................................................. 24
Power Supply Decoupling ......................................................... 25
Power Supply Sequencing ......................................................... 25
Interfacing Examples ...................................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
2/08—Rev. 0 to Rev. A
Added LFCSP Package ....................................................... Universal
Change to DC Crosstalk Parameter ............................................... 4
Change to Power Dissipation Unloaded (P) Parameter .............. 5
Added t
23
Parameter ......................................................................... 6
Change to Figure 4 ........................................................................... 7
Change to Table 5 Summary ........................................................... 9
Added Figure 8 ................................................................................ 10
Changes to Table 6 .......................................................................... 10
Changes to Calibration Section .................................................... 18
Changes to Reset Function Section .............................................. 19
Added Packet Error Checking Section ........................................ 22
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
10/07—Revision 0: Initial Version
AD5360/AD5361
Rev. A | Page 3 of 28
GENERAL DESCRIPTION
The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a
single 52-lead LQFP or 56-lead LFCSP package. They provide
buffered voltage outputs with a span four times the reference
voltage. The gain and offset of each DAC can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into two groups of eight DACs, and the output range of
each group can be independently adjusted by an offset DAC.
The AD5360/AD5361 offer guaranteed operation over a wide
supply range with V
SS
from −4.5 V to −16.5 V and V
DD
from
+8 V to +16.5 V. The output amplifier headroom requirement
is 1.4 V.
The AD5360/AD5361 have a high speed 4-wire serial interface,
which is compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to
50 MHz. All the outputs can be updated simultaneously by
taking the
LDAC
input low. Each channel has a programmable
gain register and an offset adjust register.
Each DAC output is amplified and buffered on-chip with
respect to an external SIGGNDx input. The DAC outputs can
also be switched to SIGGNDx via the
CLR
pin.

AD5360BCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-CH 16-bit Serial bipolar IC
Lifecycle:
New from this manufacturer.
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