AD5360/AD5361
Rev. A | Page 22 of 28
SPI READBACK MODE
The AD5360/AD5361 allow data readback via the serial inter-
face from every register directly accessible to the serial interface,
which is all registers except the X2A, X2B, and DAC data
registers. To read back a register, it is first necessary to tell the
AD5360/AD5361 which register is to be read. This is achieved
by writing a word whose first two bits are the Special Function
Code 00 to the device. The remaining bits then determine if the
operation is a readback and which register is to be read back, or
if it is a write to of the special function registers, such as the
control register.
If a readback command is written to a special function register,
data from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three-
stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register’s data is clocked out.
See Figure 5 for the read timing diagram. Note that, due to the
timing requirements of t
22
(25 ns), the maximum speed of the
SPI interface during a read operation should not exceed 20 MHz.
REGISTER UPDATE RATES
The value of the X2A or X2B register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
The calculation is performed by a three-stage process. The first
two stages take approximately 600 ns each, and the third stage
takes approximately 300 ns. When the write to a X1, C, or M
register is complete, the calculation process begins. If the write
operation involves the update of a single DAC channel, the user
is free to write to another register provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after the completion of the first write
operation. If a group of channels is being updated by a single
write operation, the first stage calculation is repeated for each
channel, taking 600 ns per channel. In this case, the user should
not complete the next write operation until this time has elapsed.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5360/AD5361 offer the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5360/AD5361 should generate an 8-bit
checksum using the polynomial C(x) = x
8
+ x
2
+ x
1
+1. The
checksum is added to the end of the data word, and 32 data bits
are sent to the AD5360/AD5361 before taking
SYNC
high. If
the AD5360/AD5361 see a 32-bit data frame, they perform the
error check when
SYNC
goes high. If the checksum is valid, the
data is written to the selected register. If the checksum is invalid,
the data is ignored, the packet error check output (
PEC
) goes
low, and Bit 3 of the control register is set. After reading the
control register, the error flag is cleared automatically and
PEC
goes high again.
05761-029
UPDATE ON SYNC HIGH
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
PEC GOES LOW IF
ERROR CHECK FAILS
SCLK
SDI
YNC
SCLK
SDI
YNC
PEC
MSB
D23
LSB
D0
MSB
D31
LSB
D8
24-BIT DATA
24-BIT DATA
8-BIT CHECKSUM
D7 D0
24-BIT DATA TRANSFER—NO ERROR CHECKING
24-BIT DATA TRANSFER WITH ERROR CHECKING
Figure 24. SPI Write with and Without Error Checking
