AD5360/AD5361
Rev. A | Page 20 of 28
MONITOR FUNCTION
The AD5360/AD5361 contain a channel monitor function
that consists of an analog multiplexer addressed via the serial
interface, allowing any channel output to be routed to this pin
for monitoring using an external ADC. In addition, two monitor
inputs, MON_IN0 and MON_IN1, are provided, which can also
be routed to MON_OUT. The monitor function is controlled by
the monitor register, which allows the monitor output to be
enabled or disabled, and selection of a DAC channel or one of
the monitor pins. When disabled, the monitor output is high
impedance, so several monitor outputs can be connected in
parallel and only one enabled at a time. Table 9 shows the
control register settings relevant to the monitor function.
Table 9. Control Register Monitor Functions
F5 F4 F3 F2 F1 F0 Function
0 X X X X X MON_OUT disabled
1 X X X X X MON_OUT enabled
1 0 0 0 0 0 MON_OUT = VOUT0
1 0 0 0 0 1 MON_OUT = VOUT1
1 0 1 1 1 1 MON_OUT = VOUT15
1 1 0 0 0 0 MON_OUT = MON_IN0
1 1 0 0 0 1 MON_OUT = MON_IN1
The multiplexer is implemented as a series of analog switches.
Because this could conceivably cause a large amount of current
to flow from the input of the multiplexer, that is, VOUTx or
MON_INx to the output of the multiplexer, MON_OUT, care
should taken to ensure that whatever is connected to the
MON_OUT pin is of high enough impedance to prevent the
continuous current limit specification from being exceeded.
Because the MON_OUT pin is not buffered, the amount of
current drawn from this pin creates a voltage drop across the
switches, which in turn leads to an error in the voltage being
monitored. Where accuracy is important, it is recommended
that the MON_OUT pin be buffered. Figure 20 shows the
typical error due to the MON_OUT current
GPIO PIN
The AD5360/AD5361 have a general-purpose I/O pin, GPIO.
This can be configured as an input or an output and read back
or programmed (when configured as an output) via the serial
interface. Typical applications for this pin include monitoring
the status of a logic signal, monitoring a limit switch, or
controlling an external multiplexer. The GPIO pin is configured
by writing to the GPIO register, which has the special function
code of 001101 (see Table 14 and Table 15 ). When Bit F1 is set,
the GPIO pin becomes an output and F0 determines whether
the pin is high or low. The GPIO pin can be set as an input by
writing 0 to both F1 and F0. The status of the GPIO pin can be
determined by initiating a read operation using the appropriate
bits in Table 16. The status of the pin is indicated by the LSB of
the register read.
POWER-DOWN MODE
The AD5360/AD5361 can be powered down by setting Bit 0 in
the control register to 1. This turns off the DACs, thus reducing
the current consumption. The DAC outputs are connected to
their respective SIGGND potentials. The power-down mode
does not change the contents of the registers, and the DACs
return to their previous voltage when the power-down bit is
cleared to 0.
THERMAL MONITORING FUNCTION
The AD5360/AD5361 can be programmed to power down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register to 1 (see Table 15) enables this function.
If the die temperature exceeds 130°C, the AD5360/AD5361
enter a temperature power-down mode, which is equivalent to
setting the power-down bit in the control register. To indicate
that the AD5360/AD5361 have entered temperature shutdown
mode, Bit 4 of the control register is set to 1. The AD5360/AD5361
remain in temperature shutdown mode, even if the die tempera-
ture falls, until Bit 1 in the control register is cleared to 0.
TOGGLE MODE
The AD5360/AD5361 have two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a microprocessor, which would otherwise have to
write to each channel individually. When the user writes to
either the X1A, X2A, M, or C register, the calculation engine
takes a certain amount of time to calculate the appropriate X2A
or X2B values. If the application only requires that the DAC
output switch between two levels, such as a data generator, any
method that reduces the amount of calculation time encoun-
tered is advantageous. For the data generator example, the user
should set the high and low levels for each channel once, by
writing to the X1A and X1B registers. The values of X2A and
X2B are calculated and stored in their respective registers. The
calculation delay, therefore, only happens during the setup
phase, that is, when programming the initial values. To toggle a
DAC output between the two levels, it is only required to write
to the relevant
A
/B select register to set the MUX 2 register bit.
Furthermore, because there are eight MUX 2 control bits per
register, it is possible to update eight channels with a single
write. shows the bits that correspond to each DAC
output.
Table 17
