AD5360/AD5361
Rev. A | Page 13 of 28
0.50
0.45
0.40
0.35
0.30
0.25
–40 80
TEMPERATURE (°C)
I
CC
(mA)
–20 0 20 6040
DV
CC
= +5.5V
DV
CC
= +3.6V
DV
CC
= +2.5V
V
SS
= –12V
V
DD
= +12V
V
REF
= +3V
05761-018
Figure 15. I
CC
vs. Temperature
8.0
7.5
7.0
6.5
6.0
–40 80
TEMPERATURE (°C)
I
DD
/I
SS
(mA)
–20 0 20 6040
V
SS
= –12V
V
DD
= +12V
V
REF
= +3V
I
SS
I
DD
05761-019
Figure 16. I
DD
/I
SS
vs. Temperature
14
12
10
8
6
4
2
0
7.00 7.25 7.50
7.75 8.00
V
DD
= 15V
V
SS
= 15V
T
A
= 25°C
NUMBER OF UNITS
I
DD
(mA)
0
5761-020
Figure 17. Typical I
DD
Distribution
DV
CC
= 5V
T
A
= 25°C
05761-021
6
0
0.48 0.58
I
CC
(mA)
NUMBER OF UNITS
5
4
3
2
1
0.50 0.52 0.54 0.56
Figure 18. Typical I
CC
Distribution
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
–40 –25 –10 5 20 35 50 65 80
05761-027
VOLTAGE (V)
TEMPERATURE (°C)
Figure 19. TEMP_OUT Voltage vs. Temperature
MON_OUT CURRENT (mA)
VOUTx – MON_OUT (V)
05761-026
1.0
–1.0
–1.0 1.0
0
0.5
–0.5
–0.5 0 0.5
FULL-SCALE
ZERO-SCALE
MIDSCALE
Figure 20. (VOUTx − MON_OUT Voltage) vs. MON_OUT Current
AD5360/AD5361
Rev. A | Page 14 of 28
TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity, or relative accuracy, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in millivolts, when the
channel is at its minimum value. Zero-scale error is mainly due
to offsets in the output amplifier.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.
Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in millivolts, when
the channel is at its maximum value. It does not include zero-
scale error.
Gain Error
Gain error is the difference between full-scale error and zero-
scale error. It is expressed in millivolts.
Gain Error = Full-Scale ErrorZero-Scale Error
VOUT Temperature Coefficient
This includes output error contributions from linearity, offset,
and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
DC Crosstalk
The DAC outputs are buffered by op amps that share common
V
DD
and V
SS
power supplies. If the dc load current changes in
one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple V
DD
and V
SS
terminals are
provided to minimize dc crosstalk.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data between
0x7FFF and 0x8000 (AD5360) or 0x1FFF and 0x2000 (AD5361).
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from the reference input of one DAC that appears at the
output of another DAC operating from another reference. It is
expressed in decibels and measured at midscale.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.
Digital Crosstalk
Digital crosstalk is defined as the glitch impulse transferred to
the output of one converter due to a change in the DAC register
code of another converter and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the devices digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUTx pins. It can also be coupled along the supply and
ground lines. This noise is digital feedthrough.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading all
DACs to midscale and measuring noise at the output. It is
measured in nV/√Hz.
AD5360/AD5361
Rev. A | Page 15 of 28
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE
The AD5360/AD5361 contain 16 DAC channels and 16 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit resistor-string DAC in the case of
the AD5360 and a 14-bit DAC in the case of the AD5361,
followed by an output buffer amplifier. The resistor-string
section is simply a string of resistors, of equal value, from
VREF0 or VREF1 to AGND. This type of architecture
guarantees DAC monotonicity. The 16-/14-bit binary digital
code loaded to the DAC register determines at which node
on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the
DAC output voltage by 4. The nominal output span is 12 V
with a 3 V reference and 20 V with a 5 V reference.
CHANNEL GROUPS
The 16 DAC channels of the AD5360/AD5361 are arranged into
two groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 derives its refer-
ence voltage from VREF1. Each group has its own signal
ground pin.
Table 6. AD5360/AD5361 Registers
Register Name Word Length in Bits Description
X1A (group) (channel) 16 (14) Input Data Register A, one for each DAC channel.
X1B (group) (channel) 16 (14) Input Data Register B, one for each DAC channel.
M (group) (channel) 16 (14) Gain trim register, one for each DAC channel.
C (group) (channel) 16 (14) Offset trim register, one for each DAC channel.
X2A (group) (channel) 16 (14)
Output Data Register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
X2B (group) (channel) 16 (14)
Output Data Register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.
DAC (group) (channel)
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable or directly writable.
OFS0 14 Offset DAC 0 data register, sets offset for Group 0.
OFS1 14 Offset DAC 1 data register, sets offset for Group 1.
Control 5 Control register.
Monitor 6 Monitor enable and configuration register.
GPIO 2 GPIO configuration register.
Table 7. AD5360/AD5361 Input Register Default Values
Register Name AD5360 Default Value AD5361 Default Value
X1A, X1B 0x8000 0x2000
M 0xFFFF 0x3FFF
C 0x8000 0x2000
OFS0, OFS1 0x2000 0x2000
Control 0x00 0x00
A/B Select 0 and A/B Select 1
0x00 0x00

AD5360BCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-CH 16-bit Serial bipolar IC
Lifecycle:
New from this manufacturer.
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