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AD5360BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
AD5360/AD5361
Rev. A | Page 4 of 28
SPECIFICATIONS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −16.5 V to −4.5 V; V
REF
= 5 V; AGND = DGND = SIGGND = 0 V; R
L
= open circuit;
gain (M), offset (C), and DAC offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter B Version
1
Unit Test Conditions/Comments
ACCURACY
Resolution
AD5360 16 Bits
AD5361 14 Bits
Relative Accuracy
AD5360 ±4 LSB max
AD5361 ±1 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed monotonic by design over temperature
Zero-Scale Error ±15 mV max Before calibration
Full-Scale Error ±20 mV max Before calibration
Gain Error 0.1 % FSR Before calibration
Zero-Scale Error
2
1 LSB typ After calibration
Full-Scale Error
2
1 LSB typ After calibration
Span Error of Offset DAC ±75 mV max
See the
Offset DACS section for details
VOUTx
3
Temperature Coefficient 5 ppm FSR/°C typ Includes linearity, offset, and gain drift
DC Crosstalk
4
180 μV max Typically 20 μV; measured channel at midscale, full-scale
change on any other channel
REFERENCE INPUTS (VREF0, VREF1)
2
VREF Input Current ±10 μA max Per input; typically ±30 nA
VREF Range
2
2/5 V min/max ±2% for specified operation
SIGGND INPUT (SIGGND0 to SIGGND1)
4
DC Input Impedance 50 kΩ min Typically 55 kΩ
Input Range ±0.5 V max
SIGGND Gain 0.995/1.005 Min/max
OUTPUT CHARACTERISTICS
2
Output Voltage Range V
SS
+ 1.4 V min I
LOAD
= 1 mA
V
DD
− 1.4 V max I
LOAD
= 1 mA
Nominal Output Voltage Range −10 to +10 V nominal
Short-Circuit Current 15 mA max VOUTx
3
to DV
CC
, V
DD
, or V
SS
Load Current ±1 mA max
Capacitive Load 2200 pF max
DC Output Impedance 0.5 Ω max
MONITOR PIN (MON_OUT)
4
Output Impedance
DAC Output at Positive Full-Scale 1000 Ω typ
DAC Output at Negative Full-Scale 500 Ω typ
Three-State Leakage Current 100 nA typ
Continuous Current Limit 2 mA max
DIGITAL INPUTS JEDEC compliant
Input High Voltage 1.7 V min DV
CC
= 2.5 V to 3.6 V
2.0 V min DV
CC
= 3.6 V to 5.5 V
Input Low Voltage 0.8 V max DV
CC
= 2.5 V to 5.5 V
Input Current ±1 μA max
RESET
,
SYNC
, SDI, and SCLK pins
±20 μA max
CLR
,
BIN
/2SCOMP, and GPIO pins
Input Capacitance
4
10 pF max
AD5360/AD5361
Rev. A | Page 5 of 28
Parameter B Version
1
Unit Test Conditions/Comments
DIGITAL OUTPUTS (SDO,
BUSY
, GPIO,
PEC
)
Output Low Voltage 0.5 V max Sinking 200 μA
Output High Voltage (SDO) DV
CC
− 0.5 V min Sourcing 200 μA
High Impedance Leakage Current ±5 μA max SDO only
High Impedance Output Capacitance
4
10 pF typ
TEMPERATURE SENSOR (TEMP_OUT)
4
Accuracy ±1 °C typ @ 25°C
±5 °C typ −40°C < T < +85°C
Output Voltage at 25°C 1.46 V typ
Output Voltage Scale Factor 4.4 mV/°C typ
Output Load Current 200 μA max Current source only
Power-On Time 10 ms typ To within ±5°C
POWER REQUIREMENTS
DV
CC
2.5/5.5 V min/max
V
DD
8/16.5 V min/max
V
SS
−4.5/−16.5 V min/max
Power Supply Sensitivity
4
∆ Full Scale/∆ V
DD
−75 dB typ
∆ Full Scale/∆ V
SS
−75 dB typ
∆ Full Scale/∆ DV
CC
−90 dB typ
DI
CC
2 mA max V
CC
= 5.5 V, V
IH
= DV
CC
, V
IL
= GND
I
DD
10 mA max Outputs unloaded
I
SS
10 mA max Outputs unloaded
Power-Down Mode Bit 0 in the Control Register is 1
DI
CC
5 μA typ
I
DD
35 μA typ
I
SS
−35 μA typ
Power Dissipation
Power Dissipation Unloaded (P) 245 mW max V
SS
= −12 V, V
DD
= +12 V, DV
CC
= 2.5 V
Junction Temperature 130 °C max T
J
= T
A
+ P
TOTAL
× θ
JA
1
Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
2
Specifications are guaranteed for a 5 V reference only.
3
VOUTx refers to any of VOUT0 to VOUT15.
4
Guaranteed by design and characterization, not production tested.
AC CHARACTERISTICS
DV
CC
= 2.5 V; V
DD
= 15 V; V
SS
= −15 V; V
REF
= 5 V; AGND = DGND = SIGGND = 0 V; C
L
= 200 pF; R
L
= 10 kΩ; gain (M), offset (C), and
DAC offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter B Version
1
Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
1
Output Voltage Settling Time 20 μs typ Full-scale change
30 μs max DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/μs typ
Digital-to-Analog Glitch Energy 5 nV-s typ
Glitch Impulse Peak Amplitude 10 mV max
Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 10 nV-s typ
Digital Crosstalk 0.2 nV-s typ
Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V
1
Guaranteed by design and characterization, not production tested.
AD5360/AD5361
Rev. A | Page 6 of 28
TIMING CHARACTERISTICS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −8 V to −16.5 V; V
REF
= 5 V; AGND = DGND = SIGGND = 0 V; C
L
= 200 pF to GND;
R
L
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3. SPI Interface (See Figure 4 and Figure 5)
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Description
t
1
20 ns min SCLK cycle time
t
2
8 ns min SCLK high time
t
3
8 ns min SCLK low time
t
4
11 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
20 ns min
Minimum SYNC
high time
t
6
10 ns min
24th SCLK falling edge to SYNC
rising edge
t
7
5 ns min Data setup time
t
8
5 ns min Data hold time
t
9
3
42 ns max
SYNC
rising edge to BUSY falling edge
t
10
1/1.5 μs typ/max
BUSY
pulse width low (single-channel update); see Table 8
t
11
600 ns max Single-channel update cycle time
t
12
20 ns min
SYNC
rising edge to LDAC falling edge
t
13
10 ns min
LDAC
pulse width low
t
14
3 μs max
BUSY
rising edge to DAC output response time
t
15
0 ns min
BUSY
rising edge to LDAC falling edge
t
16
3 μs max
LDAC
falling edge to DAC output response time
t
17
20/30 μs typ/max DAC output settling time
t
18
140 ns max
CLR
/RESET pulse activation time
t
19
30 ns min
RESET
pulse width low
t
20
400 μs max
RESET
time indicated by BUSY low
t
21
270 ns min
Minimum SYNC
high time in readback mode
t
22
4
25 ns max SCLK rising edge to SDO valid
t
23
80 ns max
RESET
rising edge to BUSY falling edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 2 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
This is measured with the load circuit shown in Figure 2
.
4
This is measured with the load circuit shown in Figure 3
.
TO
OUTPUT
PIN
C
L
50pF
R
L
2.2k
Ω
V
OL
DV
CC
05761-008
V
OH
(MIN) – V
OL
(MAX)
2
200µA I
OL
200µA I
OH
T
O OUTPUT
PIN
C
L
50pF
0
5761-009
Figure 2. Load Circuit for
BUSY
Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

AD5360BCPZ

Mfr. #:
Buy AD5360BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-CH 16-bit Serial bipolar IC
Lifecycle:
New from this manufacturer.
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