AD5360/AD5361
Rev. A | Page 25 of 28
Table 16. Address Codes for Data Readback
1
F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read
0 0 0
Bit F12 to Bit F7 select channel to be read back,
Channel 0 = 001000 to Channel 15 = 010111
X1A Register
0 0 1 X1B Register
0 1 0 C Register
0 1 1 M Register
1 0 0 0 0 0 0 0 1 Control Register
1 0 0 0 0 0 0 1 0 OFS0 Data Register
1 0 0 0 0 0 0 1 1 OFS1 Data Register
1 0 0 0 0 0 1 0 0 Reserved
1 0 0 0 0 0 1 1 0
A
/B Select Register 0
1 0 0 0 0 0 1 1 1
A
/B Select Register 1
1 0 0 0 0 1 0 0 0 Reserved
1 0 0 0 0 1 0 0 1 Reserved
1 0 0 0 0 1 0 1 0 Reserved
1 0 0 0 0 1 0 1 1 GPIO Read (Data in F0)
2
1
F6 to F0 are don’t cares for the data readback function.
2
F6 to F0 should be 0 for GPIO read.
Table 17. DACs Selected by
A
/B Select Registers
A
/B Select
Register
Bits
1
F7 F6 F5 F4 F3 F2 F1 F0
0 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
1 DAC15 DAC14 DAC13 DAC12 DAC11 DAC10 DAC9 DAC8
1
If the bit is 0, Register X2A is selected. If the bit is 1, Register X2B is selected.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5360/AD5361 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5360/AD5361 are in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (V
SS
, V
DD
, DV
CC
),
it is recommended to tie these pins together and to decouple
each supply once.
The AD5360/AD5361 should have ample supply decoupling of
10 μF in parallel with 0.1 μF on each supply located as close to
the package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-
tor should have low effective series resistance (ESR) and effective
series inductance (ESI), such as the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching.
Digital lines running under the device should be avoided
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5360/AD5361 to
avoid noise coupling. The power supply lines of the AD5360/
AD5361 should use as large a trace as possible to provide low
impedance paths and reduce the effects of glitches on the power
supply line. Fast switching digital signals should be shielded
with digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs. It is
essential to minimize noise on all VREFx lines.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but this is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5360/AD5361, it is
important that the AGND and DGND pins be connected to the
relevant ground plane before the positive or negative supplies
are applied. In most applications, this is not an issue because the
ground pins for the power supplies are connected to the ground
pins of the AD5360/AD5361 via ground planes. Where the
AD5360/AD5361 are used in a hot-swap card, care should be
taken to ensure that the ground pins are connected to the
supply grounds before the positive or negative supplies are
connected. This is required to prevent currents from flowing in
directions other than toward an analog or digital ground.
