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813252CKI-02LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Jitter Attenuator & FemtoClock
®
Multiplier
ICS813252I-02
DATA SHEET
ICS813252CKI-02 REVISION A AUGUST 4, 2016 1 ©2016 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The ICS813252I-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series. The fi rst
stage is a VCXO PLL that is optimized to provide reference clock
jitter attenuation. The second stage is a FemtoClock
®
frequency
multiplier that provides the low jitter, high frequency Ethernet
output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter
requirements. Pre-divider and output divider multiplication ratios
are selected using device selection control pins. The multiplication
ratios are optimized to support most common clock rates used in
PDH, SONET and Ethernet applications. The VCXO requires the
use of an external, inexpensive pullable crystal. The VCXO uses
external passive loop fi lter components which allows confi guration
of the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-VFQFN package and
supports industrial temperature range.
PIN ASSIGNMENT
FEATURES
• Two LVPECL outputs
Each output supports independent frequency selection at
25MHz, 125MHz, 156.25MHz and 312.5MHz
• Two differential inputs support the following input types: LVPE-
CL, LVDS, LVHSTL, SSTL, HCSL
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a low-
cost pullable fundamental mode VCXO crystal
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking
using external loop fi lter connection
• FemtoClock frequency multiplier provides low jitter, high fre-
quency output
• Absolute pull range: 50ppm
• FemtoClock VCO frequency: 625MHz
•
RMS phase jitter @ 125MHz, using a 25MHz crystal
(10kHz – 20MHz): 1.3ps (maximum)
• 3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement device use 813N252CKI-02LF
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
EE
nQB
QB
VCCO
nQA
QA
VEE
ODASEL_0
ICS813252I-02
PDSEL_2
PDSEL_1
PDSEL_0
VCC
VCCA
ODBSEL_1
ODBSEL_0
ODASEL_1
nCLK1
CLK1
VCC
nCLK0
CLK0
XTAL_OUT
XTAL_IN
VCCX
LF1
LF0
ISET
VEE
CLK_SEL
VCC
RESERVED
VEE
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
OBSOLETE
ICS813252CKI-02 REVISION A AUGUST 4, 2016 2 ©2016 Integrated Device Technology, Inc.
ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
BLOCK DIAGRAM
Charge
Pump
VCXO
Phase
Detector
Output Divider
00 = 25
(default)
01 = 5
10 = 4
11 = 2
Output Divider
00 = 25
(default)
01 = 5
10 = 4
11 = 2
VCXO Feedback Divider
÷3125
VCXO Input
Pre-Divider
VCXO Jitter Attenuation PLL
XTAL_IN
XTAL_OUT
LF1
LF0
ISET
Loop
Filter
ODASEL_[1:0]
CLK0
PDSEL_[2:0]
nCLK0
0
1
25MHz
2
2
QB
nQB
ODBSEL_[1:0]
FemtoClock PLL
625MHz
000 = 1
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
CLK1
nCLK1
CLK_SEL
Pulldown
Pullup
QA
nQA
111 = 19440
(default)
ICS813252CKI-02 REVISION A AUGUST 4, 2016 3 ©2016 Integrated Device Technology, Inc.
ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51 kΩ
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 2 LF1, LF0
Analog Input/
Output
Loop fi lter connection node pins.
LF0 is the output. LF1 is the input.
3 ISET
Analog Input/
Output
Charge pump current setting pin.
4, 8, 18, 24 V
EE
Power Negative supply pins.
5 CLK_SEL Input Pulldown
Input clock select. When HIGH selects CLK1/nCLK1.
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
6, 12, 27 V
CC
Power Core power supply pins.
7 RESERVED Reserved Reserved pin. Do not connect.
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
13 V
CCA
Power Analog supply pin.
14,
15
ODBSEL_1,
ODBSEL_0
Input Pulldown
Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVT-
TL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input Pulldown
Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVT-
TL interface levels.
19, 20 QA, nQA Output Differential Bank A clock outputs. LVPECL interface levels.
21 V
CCO
Power Output power supply pin.
22, 23 QB, nQB Output Differential Bank B clock outputs. LVPECL interface levels.
25 nCLK1 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 bias voltage when left fl oating.
26 CLK1 Input Pulldown Non-inverting differential clock input.
28 nCLK0 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 bias voltage when left fl oating.
29 CLK0 Input Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
32 V
CCX
Power Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

813252CKI-02LF

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Description:
IC MULTIPLIER VCXO PLL 32-VFQFPN
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