813252CKI-02LF Datasheet 813252CKI-02LF, 813252CKI-02LFT | P10-P12

ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK

MULTIPLIER

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter perfor-

mance, power supply isolation is required. The ICS813252I-02

provides separate power supplies to isolate any high switch-

ing noise from the outputs to the internal PLL. V

, V

CCX

, V

CCA

and V

CCO

should be individually connected to the power supply

plane through vias, and 0.01µF bypass capacitors should be

used for each pin. Figure 1 illustrates this for a generic V

and also shows that V

CCA

requires that an additional 10Ω resistor

along with a 10µF bypass capacitor be connected to the V

CCA

pin.

FIGURE 1. POWER SUPPLY FILTERING

Figure 2 shows how a differential input can be wired to accept single

ended levels. The reference voltage V

REF

= V

/2 is generated by

the bias resistors R1 and R2. The bypass capacitor (C1) is used to

help ﬁ lter noise on the DC bias. This bias circuit should be located

as close to the input pin as possible. The ratio of R1 and R2 might

need to be adjusted to position the V

REF

in the center of the input

voltage swing. For example, if the input clock swing is 2.5V and V

= 3.3V, R1 and R2 value should be adjusted to set V

REF

at 1.25V.

The values below are for when both the single-ended swing and V

are at the same voltage. This conﬁ guration requires that the sum of

the output impedance of the driver (Ro) and the series resistance

(Rs) equals the transmission line impedance. In addition, matched

termination at the input will attenuate the signal in half. This can be

done in one of two ways. First, R3 and R4 in parallel should equal the

transmission line impedance. For most 50 applications, R3 and R4

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

can be 100Ω. The values of the resistors can be increased to reduce

the loading for slower and weaker LVCMOS driver. When using

single ended signaling, the noise rejection beneﬁ ts of differential

signaling are reduced. Even though the differential input can handle

full rail LVCMOS signaling, it is recommended that the amplitude

be reduced. The datasheet speciﬁ es a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V

cannot be less than

-0.3V and V

cannot be more than V

+ 0.3V. Though some of the

recommended components might not be used, the pads should be

placed in the layout. They can be utilized for debugging purposes.

The datasheet speciﬁ cations are characterized and guaranteed by

using a differential signal.

ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK

MULTIPLIER

FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A

3.3V LVPECL DRIVER

FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A

3.3V LVPECL DRIVER

FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. V

SWING

and V

must meet the VPP and

CMR input requirements. Figures 3A to 3F show interface examples

for the CLK/nCLK input driven by the most common driver types.

The input interfaces suggested here are examples only. Please

consult with the vendor of the driver component to conﬁ rm the

FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN

IDT OPEN EMITTER LVHSTL DRIVER

driver termination requirements. For example in Figure 3A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A

3.3V HCSL DRIVER

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiver

CLK

nCLK

3.3V

FIGURE 3F. CLK/nCLK INPUT DRIVEN BY A

2.5V SSTL DRIVER

ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK

MULTIPLIER

INPUTS:

CLK/nCLK INPUTS

For applications not requiring the use of the differential input, both

CLK and nCLK can be left ﬂ oating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to ground.

LVCMOS C

ONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

OUTPUTS:

LVPECL OUTPUTS

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

All unused LVPECL outputs can be left ﬂ oating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left ﬂ oating or terminated.

FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)

VFQFN EPAD THERMAL RELEASE PATH

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on

the package, as shown in Figure 4. The solderable area on the PCB,

as deﬁ ned by the solder mask, should be at least the same size/

shape as the exposed pad/slug area on the package to maximize

the thermal/electrical performance. Sufﬁ cient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern

must be connected to ground through these vias. The vias act as

“heat pipes”. The number of vias (i.e. “heat pipes”) are application

speciﬁ c and dependent upon the package power dissipation as well

as electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern.

It is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This

is desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and

the land pattern. Note: These recommendations are to be used as a

guideline only. For further information, refer to the Application Note

on the Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadfame Base Package, Amkor Technology.

SOLDERSOLDER

PINPIN EXPOSED HEAT SLUG

PIN PAD PIN PADGROUND PLANE LAND PATTERN

(GROUND PAD)

THERMAL VIA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

813252CKI-02LF

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813252CKI-02LF

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