ICS813252CKI-02 REVISION A AUGUST 4, 2016 16 ©2016 Integrated Device Technology, Inc.
ICS813252I-02 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813252I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813252I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 235mA = 814.275mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.465V, with all outputs switching) = 814.275mW + 60mW = 874.275mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming no air fl ow
and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.874W * 37°C/W = 117.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ
JA
FOR 32 LEAD VFQFN, FORCED CONVECTION
θ
JA
vs. 0 Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W
