GDDR6 SGRAM
MT61K256M32
2 Channels x 256 Meg x 16 I/O, 2 Channels x 512 Meg x 8 I/O
Features
• V
DD
= V
DDQ
= 1.35V ±3% and 1.25V ±3%
• V
PP
= 1.8V –3%/+6%
• Data rate: 12 Gb/s, 14 Gb/s, 16 Gb/s
• 2 separate independent channels (x16)
• x16/x8 and 2-channel/pseudo channel (PC) mode
configurations set at reset
• Single ended interfaces per channel for command/
address (CA) and data
• Differential clock input CK_t/CK_c for CA per 2
channels
• One differential clock input WCK_t/WCK_c per
channel for data (DQ, DBI_n, EDC)
• Double data rate (DDR) command/address (CK)
• Quad data rate (QDR) and double data rate (DDR)
data (WCK), depending on operating frequency
• 16n prefetch architecture with 256 bits per array
read or write access
• 16 internal banks
• 4 bank groups for
t
CCDL = 3
t
CK and 4
t
CK
• Programmable READ latency
• Programmable WRITE latency
• Write data mask function via CA bus with single and
double byte mask granularity
• Data bus inversion (DBI) and CA bus inversion
(CABI)
• Input/output PLL
• CA bus training: CA input monitoring via DQ/
DBI_n/EDC signals
• WCK2CK clock training with phase information via
EDC signals
• Data read and write training via read FIFO (depth =
6)
• Read/write data transmission integrity secured by
cyclic redundancy check using half data rate CRC
• Programmable CRC READ latency
• Programmable CRC WRITE latency
• Programmable EDC hold pattern for CDR
• RDQS mode on EDC pins
• Low power modes
• On‐chip temperature sensor with read‐out
• Auto precharge option for each burst access
• Auto refresh mode (32ms, 16k cycles) with per-bank
and per-2-bank refresh options
• Temperature sensor controlled self refresh rate
• Digital
t
RAS lockout
• On‐die termination (ODT) for all high‐speed inputs
• Pseudo open drain (POD135 and POD125) compati-
ble outputs
• ODT and output driver strength auto calibration
with external resistor ZQ pin (120Ω)
• Internal V
REF
with DFE for data inputs, with input
receiver characteristics programmable per pin
• Selectable external or internal V
REF
for CA inputs;
programmable V
REF
offsets for internal V
REF
• Vendor ID for device identification
• IEEE 1149.1 compliant boundary scan
• 180-ball BGA package
• Lead-free (RoHS-compliant) and halogen-free
packaging
• T
C
= 0°C to +95°C
Options
1
Marking
• Organization
– 256 Meg × 32 (words × bits) 256M32
• FBGA package
– 180-ball (12.0mm × 14.0mm) JE
• Timing – maximum data rate
– 12 Gb/s -12
– 14 Gb/s -14
– 16 Gb/s -16
• Operating temperature
– Commercial (0°C ≤ T
C
≤ +95°C) None
• Revision A
Note:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Features
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
