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MT61K256M32JE-14:A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Figure 9: System View for x16 and x8 Modes
CK_t, CK_c
RESET_n
CA[9:0]_X, CABI_n_X
EDC0_X
WCK0_t_X, WCK0_c_X
WCK1_t_X, WCK1_c_X
EDC1_X
DQ[15:8]_X, DBI1_n_X
CKE_n_X
CA[9:0]_Y, CABI_n_Y
EDC1_Y
WCK1_t_Y, WCK1_c_Y
WCK0_t_Y, WCK0_c_Y
DQ[15:8]_Y, DBI1_n_Y
EDC0_Y
DQ[7:0]_Y, DBI0_n_Y
CKE_n_Y
CK_t, CK_c
RESET_n
ADD/
CMD
(Ch A)
(Ch B)
CA[9:0]_X, CABI_n_X
EDC1_A
EDC0_X
WCK_t_X, WCK_c_X
DQ[7:0]_X, DBI0_n_X
DQ[7:0]_X, DBI0_n_X
EDC1_X
DQ[15:8]_X, DBI1_n_X
EDC0_A
CKE_n_X
ADD/
CMD
CA[9:0]_Y, CABI_n_Y
EDC0_B
Byte 1_B
EDC1_Y
WCK_t_Y, WCK_c_Y
DQ[15:8]_Y, DBI1_n_Y
EDC0_Y
DQ[7:0]_Y, DBI0_n_Y
EDC1_B
CKE_n_Y
WCK_A
WCK_B
Byte 1_A
Byte 0_B
GDDR6
x16
Byte 0_A
Channel XChannel Y
Host
Host
Channel XChannel Y
ADD/
CMD
Byte 1_B
EDC0_B
EDC1_B
ADD/
CMD
Byte 0_A
EDC1_A
EDC0_A
WCK_B
WCK_A
GDDR6
x8
GDDR6
x8
ADD/
CMD
EDC1_A
EDC0_A
ADD/
CMD
EDC0_B
Byte 1_B
EDC1_B
WCK_A
WCK_B
Byte 0_A
(Ch A)
(Ch B)
(Ch B)
(Ch A)
Figure 10 clarifies the use of x8 mode and how the bytes are enabled/disabled to give
the controller the view of the same bytes that a controller sees with a single x16 device.
For a 16-bit channel using two devices in a clamshell design, byte 0 comes from channel
A from the top device and byte 1 comes from channel B from the bottom device and will
look equivalent at the controller to a x16 mode.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Functional Description
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Figure 10: Byte Orientation in Clamshell Topology
x8
x8
Legend:
Data
ADD/CMD
CK, WCK
x8 top
x8 bottom
Ch A
Byte
0
Ch B
Byte
1
Ch A
Byte
0
Ch B
Byte
1
Ch A
Byte
0
Ch B
Byte
1
Ch A
Byte
1
Ch B
Byte
0
+ =
Pseudo-Channel Mode
GDDR6 has been optimized for a 32B access across a 16-bit channel by providing a
unique CA bus to each 16-bit-wide channel. For applications requiring fewer CA pins,
GDDR6 includes support for a pseudo-channel (PC) mode where CA[9:4], CKE_n, and
CABI_n on each channel are connected to a common bus, while CA[3:0] of each chan-
nel are connected to a separate bus. The command truth table is organized such that in
PC mode the same command is decoded in both pseudo-channels, but READ and
WRITE commands support a unique column address to each pseudo-channel. In PC
mode, CKE_n and CABI_n are also shared across pseudo-channels.
In PC mode, the only difference in the DRAM is that termination on CA[9:4], CKE_n,
and CABI_n can be configured differently from CA[3:0]. PC mode can be selected during
initialization by driving CA6 = LOW on both channels when RESET_n is driven HIGH.
Figure 11: CA Pins in Pseudo-Channel Mode
GDDR6
CA[3:0]_A
CA[9:4]_A, CABI_n_A, CKE_n_A
CA[9:4]_B, CABI_n_B, CKE_n_B
CA[3:0]_B
CA[3:0]_A
CA[9:4], CABI_n, CKE_n
CA[3:0]_B
Pseudo-Channel Mode Controller
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Functional Description
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Operating Conditions
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may ad-
versely affect reliability.
Table 5: Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
V
DD
Voltage on V
DD
pin relative to V
SS
–0.3 2.0 V 1
V
DDQ
Voltage on V
DDQ
pin relative to V
SS
–0.3 2.0 V 1
V
PP
Voltage on V
PP
pin relative to V
SS
–0.3 2.3 V 2
V
IN
/V
OUT
Voltage on any pins relative to V
SS
–0.3 2.0 V
T
STG
Storage temperature –55 +125 °C
Notes:
1. V
DD
and V
DDQ
must be within 300mV of each other at all times the device is powered‐
up.
2. V
PP
must be equal or greater than V
DD
and V
DDQ
at all times the device is powered‐up.
DC and AC Operating Conditions
The interface of GDDR6 with 1.35V V
DDQ
will follow the POD135 Standard (JESD8-21),
Class D; The interface with 1.25V V
DDQ
will follow the POD125 Standard (JESD8-30),
Class A. All AC and DC values are referenced to the ball.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Operating Conditions
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
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MT61K256M32JE-14:A

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Manufacturer:
Micron
Description:
DRAM GDDR6 8G 256MX32 FBGA
Lifecycle:
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