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MT61K256M32JE-14:A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Table 6: DC Operating Conditions
Symbol Parameter
POD135 POD125
Unit NotesMin Typ Max Min Typ Max
V
DD
Device supply voltage 1.3095 1.35 1.3905 1.2125 1.25 1.2875 V 1, 2
V
DDQ
Output supply voltage 1.3095 1.35 1.3905 1.2125 1.25 1.2875 V 1, 2
V
PP
Pump voltage 1.746 1.8 1.908 1.746 1.8 1.908 V 2
V
REFD
Reference voltage for DQ and DBI_n 0.69 × V
DDQ
– 0.71 × V
DDQ
0.69 × V
DDQ
− 0.71 × V
DDQ
V 3, 4
V
REFD2
0.49 × V
DDQ
– 0.51 × V
DDQ
0.49 × V
DDQ
− 0.51 × V
DDQ
V 3, 4, 5
V
REFC
Reference voltage for CA 0.69 × V
DDQ
– 0.71 × V
DDQ
0.69 × V
DDQ
− 0.71 × V
DDQ
V 3, 6
V
REFC2
0.49 × V
DDQ
– 0.51 × V
DDQ
0.49 × V
DDQ
− 0.51 × V
DDQ
V 3, 6, 7
V
IHA(DC)
DC input logic HIGH voltage with V
REFC
for CA V
REFC
+
0.135
– – V
REFC
+
0.125
− − V
V
ILA(DC)
DC input logic LOW voltage with V
REFC
for CA – – V
REFC
‐ 0.135 − − V
REFC
- 0.125 V
V
IHA2(DC)
DC input logic HIGH voltage with V
REFC2
for CA V
REFC2
+
0.27
– – V
REFC2
+
0.25
− − V
V
ILA2(DC)
DC input logic LOW voltage with V
REFC2
for CA – – V
REFC2
‐ 0.27 − − V
REFC2
- 0.25 V
V
IHD(DC)
DC input logic HIGH voltage with V
REFD
for DQ and
DBI_n
V
REFD
+ 0.09 – – V
REFD
+
0.085
− − V
V
ILD(DC)
DC input logic LOW voltage with V
REFD
for DQ and
DBI_n
– – V
REFD
‐ 0.09 − − V
REFD
- 0.085 V
V
IHD2(DC)
DC input logic HIGH voltage with V
REFD2
for DQ and
DBI_n
V
REFD2
+
0.27
– – V
REFD2
+
0.25
− − V
V
ILD2(DC)
DC input logic LOW voltage with V
REFD2
for DQ and
DBI_n
– – V
REFD2
‐ 0.27 − − V
REFD2
- 0.25 V
V
IHR
RESET_n and boundary scan input logic HIGH volt-
age; EDC and CA input logic HIGH voltage for x16/x8
mode, PC vs. 2-channel mode, CK and CA ODT select
at reset
0.8 × V
DDQ
– – 0.8 × V
DDQ
− − V 8
V
ILR
RESET_n and boundary scan input logic LOW voltage;
EDC and CA input logic LOW voltage for x16/x8
mode, PC vs. 2-channel mode, CK and CA ODT select
at reset
– – 0.2 × V
DDQ
− − 0.2 × V
DDQ
V 8
V
IN
Single ended clock input voltage level: CK_t, CK_c,
WCK_t, WCK_c
–0.30 – V
DDQ
+ 0.30 –0.30 − V
DDQ
+ 0.30 V 14
V
MP(DC)
CK_t, CK_c clock input midpoint voltage V
REFC
- 0.10 – V
REFC
+ 0.10 V
REFC
‐ 0.10 − V
REFC
+ 0.10 V 9, 12
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Operating Conditions
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Table 6: DC Operating Conditions (Continued)
Symbol Parameter
POD135 POD125
Unit NotesMin Typ Max Min Typ Max
V
IDCK(DC)
CK_t, CK_c clock input differential voltage 0.198 – – 0.18 − − V 10, 12
V
IDWCK(DC)
WCK_t, WCK_c clock input differential voltage 0.18 – – 0.165 − − V 11, 13
I
L
Input leakage current (any input 0V ≤ V
IN
≤ V
DDQ
; all
other signals not under test = 0V)
–5 – 5 −5 − 5 µA
I
OZ
Output leakage current (outputs are disabled; 0V ≤
V
OUT
≤ V
DDQ
)
–5 – 5 −5 − 5 µA
V
OL(DC)
Output logic low voltage – – 0.56 – – 0.52 V
ZQ External resistor value 115 120 125 115 120 125 Ω
Notes:
1. GDDR6 SGRAM devices are designed to tolerate PCB designs with separate V
DD
and V
DDQ
power regulators.
2. DC bandwidth is limited to 20 MHz.
3. AC noise in the system is estimated at 50mV peak-to-peak for the purpose of DRAM design.
4. The reference voltage source and control for DQ and DBI_n pins are determined by half V
REFD
, and V
REFD
level
mode register bits.
5. Programmable V
REFD
levels are not supported with V
REFD2
.
6. The reference voltage source (external or internal) is determined at power‐up; the reference voltage level is deter-
mined by half V
REFC
and the V
REFC
offset mode register bit.
7. Programmable V
REFC
offsets are not supported with V
REFC2
.
8. V
IHR
and V
ILR
apply to boundary scan input pins TDI, TMS, and TCK. V
IHR
and V
ILR
apply to EDC and CA inputs at
reset when latching default device configurations. V
IHR
and V
ILR
also apply to CA, CABI_n, CKE_n, CK, DQ, DBI_n,
EDC, and WCK inputs when boundary scan mode is active and input data are latched in the capture-DR TAP con-
troller state.
9. This provides a minimum of 0.845V to a maximum of 1.045V with POD135, and a minimum of 0.775V to a maxi-
mum of 0.975V with POD125, and is normally 70% of V
DDQ
. DRAM timings relative to CK cannot be guaranteed if
these limits are exceeded.
10. V
IDCK
is the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input
reference level for signals other than CK_t and CK_c is V
REFC
.
11. V
IDWCK
is the magnitude of the difference between the input level in WCK_t and the input level on WCK_c. The
input reference level for signals other than WCK_t and WCK_c is either V
REFC
, V
REFC2
, V
REFD
, or V
REFD2
.
12. The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and
CK_c cross. Refer to the applicable timings in the AC Timings table.
13. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which
WCK_t and WCK_c cross. Refer to the applicable timings in the AC Timings table.
14. Use V
IHR
and V
ILR
when boundary scan mode is active and input data are latched in the capture-DR TAP controller
state.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Operating Conditions
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Table 7: AC Operating Conditions (For Design Only
9
)
Symbol Parameter
POD135 POD125
Unit NotesMin Typ Max Min Typ Max
V
IHA(AC)
AC input logic HIGH voltage with V
REFC
for CA V
REFC
+ 0.18 – – V
REFC
+
0.165
− − V
V
ILA(AC)
AC input logic LOW voltage with V
REFC
for CA – – V
REFC
‐ 0.18 − − V
REFC
- 0.165 V
V
IHA2(AC)
AC input logic HIGH voltage with V
REFC2
for CA V
REFC2
+
0.36
– – V
REFC
+
0.333
− − V
V
ILA2(AC)
AC input logic LOW voltage with V
REFC2
for CA – – V
REFC2
‐ 0.36 − − V
REFC
- 0.333 V
V
IHD(AC)
AC input logic HIGH voltage with V
REFD
for DQ,
DBI_n
V
REFD
+
0.135
– – V
REFD
+
0.125
− − V
V
ILD(AC)
AC input logic LOW voltage with V
REFD
for DQ, DBI_n – – V
REFD
‐ 0.135 − − V
REFD
- 0.125 V
V
IHD2(AC)
AC input logic HIGH voltage with V
REFD2
for DQ,
DBI_n
V
REFD2
+
0.36
– – V
REFD2
+
0.333
− − V
V
ILD2(AC)
AC input logic LOW voltage with V
REFD2
for DQ,
DBI_n
– – V
REFD2
‐ 0.36 − − V
REFD2
-
0.333
V
V
IDCK(AC)
CK_t, CK_c clock differential voltage 0.36 – – 0.333 − − V 1, 3, 5
V
IDWCK(AC)
WCK_t, WCK_c clock input differential voltage 0.27 – – 0.25 − − V 1, 4, 6
V
IXCK(AC)
CK_t, CK_c clock input crossing point voltage V
REFC
- 0.108 – V
REFC
+
0.108
V
REFC
‐ 0.10 − V
REFC
+ 0.10 V 1, 2, 5
V
IXWCK(AC)
WCK_t, WCK_c clock input crossing point voltage V
REFD
- 0.09 – V
REFD
+ 0.09 V
REFC
‐ 0.09 − V
REFC
+ 0.09 V 1, 2, 6,
7
Notes:
1. For AC operations, all DC clock requirements must be satisfied as well.
2. The value of V
IXCK
and V
IXWCK
is expected to equal 70% V
DDQ
for the transmitting device and must track variations
in the DC level of the same.
3. V
IDCK
is the magnitude of the difference between the input level on CK_t and the input level on CK_c. The input
reference level for signals other than CK_t and CK_c is V
REFC
.
4. V
IDWCK
is the magnitude of the difference between the input level on WCK_t and the input level on WCK_c. The
input reference level for signals other than WCK_t and WCK_c is either V
REFC
, V
REFC2
, V
REFD
, or V
REFD2
.
5. The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and
CK_c cross. Refer to the applicable timings in the AC Timings table.
6. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which
WCK_t and WCK_c cross. Refer to the applicable timings in the AC Timings table.
7. V
REFD
is either V
REFD
or V
REFD2
.
8. Figure 13 illustrates the exact relationship between (CK_t - CK_c) or (WCK_t - WCK_c) and V
ID(AC)
, V
ID(DC)
.
9. The AC operating conditions are for DRAM design only and are valid on the silicon at the input of the receiver.
They are not intended to be measured.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Operating Conditions
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

MT61K256M32JE-14:A

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Description:
DRAM GDDR6 8G 256MX32 FBGA
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