2003 Oct 01 11
Philips Semiconductors Product specification
CD audio decoder, digital servo and filterless
DAC with integrated pre-amp and laser control
SAA7826
7.4 Data slicer and bit clock regenerator
The SAA7826 has an integrated adaptive data slicer which
is clocked at 67 MHz. The slice level is controlled by
internal current sources which are switched onto and
integrated by the external capacitor connected to the
CSLICE pin. The currents are switched under the control
of a Digital Phase-Locked loop (DPLL).
Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required.
The bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization. The
PLL loop response is illustrated in Fig.5.
For certain applications an off-track input is necessary.
This is internally connected from the servo part (its polarity
can be changed by the foc_parm1 parameter), but can be
input via pin V1 if selected by register C. If this flag is
HIGH, the SAA7826 assumes that its servo part is
following the wrong track, and will flag all incoming HF data
as incorrect.
7.5 DC offset cancellation
Unwanted DC offsets can exist within the photo-diode
signals and are defined as the DC present in the system
when the laser diode is switched off. They arise from
various sources of imperfection within the system such as
leakage in the photo diodes and offsets in the Optical
Pick-Up (OPU) circuitry. The SAA7826 is capable of
measuring these offsets and minimizing them.
7.5.1 OFFSET CANCELLATION
A number of registers are associated with the DC offset
cancellation function; these registers are given in Table 3.
The measurement time of the DC offset is regulated by
new shadow register C (bank 2). A longer time will yield
more accurate results but will result in greater
measurement durations.
New shadow register 3 (bank 3) is used to select which
diode is to be measured.
7.5.2 READING BACK THE DC OFFSET VALUE
The microcontroller reads the DC offset measurements in
order to calculate the correct cancellation value [for writing
back to new shadow register 7 (bank 3)].
This is achieved by using the STATUS pin and setting
decoder register 7 to XX10. Shadow register C (bank 3)
can then be used to control the STATUS pin output; the
register settings are given in Table 20.
Once the measurement time has been set and the diode
selected, the STATUS pin should be set to read the DC
offset ready flag [new shadow register C
(bank 3) = X01X]. This signal toggles HIGH after the
prescribed measurement time. Changing the diode
selection results in the measurement timer being
automatically reset.
The microcontroller can read back the measurement by
setting the STATUS pin to output the DC offset value
[new shadow register C (bank 3) = X10X].
The offset value is repeatedly streamed out through the
STATUS pin and is UART compatible. It should be noted
that the MSB is inverted and will require re-inverting after
the offset value has been captured. Timing information for
this signal is illustrated in Fig.6.
The final DC cancellation value (as calculated by the
microcontroller) can then be written to new shadow
register 7 (bank 3). This is a multiple write register
containing the cancellation values for all six diodes.
MGS178
handbook, halfpage
f
3. PLL, LPF
2. PLL bandwidth
1. PLL integrator
PLL
loop
response
Fig.5 Digital PLL loop response.
Points 1, 2 and 3 are all programmable via decoder register 8.
