SAA7826HL/M1A,557 Datasheet SAA7826HL/E/M1A,55, SAA7826HL/M1A,557 | P19-P21

2003 Oct 01 19

Philips Semiconductors Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7826

7.9 Audio functions

7.9.1 DE-EMPHASIS AND PHASE LINEARITY

When pre-emphasis is detected in the Q-channel

subcode, the digital filter automatically includes a

de-emphasis filter section. When de-emphasis is not

required, a phase compensation filter section will control

the phase of the digital oversampling filter to ≤±1° within

the 0 to 16 kHz band. With de-emphasis the filter is not

phase linear.

If the de-emphasis signal is set to be available at pin V5,

selected via decoder register D, then the de-emphasis

filter is bypassed.

7.9.2 DIGITAL OVERSAMPLING FILTER

For optimization of performance with an external DAC, the

SAA7826 contains a 2 to 4 times oversampling IIR filter.

The filter specification of the 4 times oversampling filter is

given in Table 5.

The attenuation does not include the sample-and-hold at

the external DAC output or the DAC post filter. When using

the oversampling filter, the output level is scaled −0.5 dB

down to avoid overflow on full-scale sine wave inputs

(0 to 20 kHz).

Table 5 Filter speciﬁcation

7.9.3 CONCEALMENT

A 1-sample linear interpolator becomes active if a single

sample is flagged as erroneous but cannot be corrected.

The erroneous sample is replaced by a level midway

between the preceding and following samples. Left and

right channels have independent interpolators. If more

than one consecutive non-correctable sample is found, the

last good sample is held. A 1-sample linear interpolation is

then performed before the next good sample; see Fig.13.

In CD-ROM modes (i.e. the external DAC interface is

selected to be in a CD-ROM format) concealment is not

executed.

7.9.4 MUTE, FULL-SCALE, ATTENUATION AND FADE

A digital level controller is present on the SAA7826 which

performs the functions of soft mute, full-scale, attenuation

and fade; these are selected via decoder register 0:

• Mute: signal reduced to 0 in a maximum of 128 steps;

3/n ms

• Attenuation: signal scaled by −12 dB

• Full-scale: ramp signal back to 0 dB level; from mute it

takes 3/n ms

• Fade: activates a 128 stage counter which allows the

signal to be scaled up or down in 0.07 dB steps

– 128 = full-scale

– 120 = −0.5 dB (i.e. full-scale if oversampling filter is

used)

–32=−12 dB

– 0 = mute.

7.9.5 PEAK DETECTOR

The peak detector measures the highest audio level

(absolute value) on positive peaks for left and right

channels. The 8 most significant bits are output in the

Q-channel data in place of the CRC bits. Bits 81 to 88

contain the left peak value (bit 88 = MSB) and bits 89 to 96

contain the right peak value (bit 96 = MSB). The values

are reset after reading Q-channel data via pin SDA.

PASS BAND STOP BAND ATTENUATION

0 to 9 kHz −≤0.001 dB

19 to 20 kHz −≤0.03 dB

− 24 kHz ≥25 dB

− 24 to 27 kHz ≥38 dB

− 27 to 35 kHz ≥40 dB

− 35 to 64 kHz ≥50 dB

− 64 to 68 kHz ≥31 dB

− 68 kHz ≥35 dB

− 69 to 88 kHz ≥40 dB

2003 Oct 01 20

Philips Semiconductors Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7826

Interpolation Hold Interpolation

MGA372

OK Error OK Error Error Error OK OK

Fig.13 Concealment mechanism.

7.10 Audio DAC interface

7.10.1 INTERNAL DYNAMIC ELEMENT MATCHING DIGITAL-TO-ANALOG CONVERTER

The onboard audio DEM DAC operates at an oversampling rate of 96f

and is designed for operation with an audio input

at 1f

. The DAC is equipped with two pairs of stereo outputs for driving medium impedance line outputs and for directly

driving low impedance headphones. A pair of analog inputs are provided to enable external audio sources to make use

of the headphone output buffers.

Audio data from the decoder part of the SAA7826 can be routed as described in Sections 7.10.1.1 and 7.10.1.2.

Table 6 Shadow register

SHADEN BITS

SHADOW

ADDRESS DATA FUNCTION RESET

(bank 1)

control of

onboard DAC

0111 0000 use external DAC or route audio data

back into onboard DAC (loopback

mode)

reset

0010 route audio data directly into onboard

DAC (non-loopback mode)

−

2003 Oct 01 21

Philips Semiconductors Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7826

7.10.1.1 Use of internal DAC

Setting shadow register 7 to 0010 routes audio data from

the decoder into the internal DAC. To enable the on-board

DAC, the DAC interface format (set by register 3) must be

set to 16-bit 1f

mode, either I

S-bus or EIAJ format.

CD-ROM mode can also be used if interpolation is not

required. The serial data output pins for interfacing with an

external DAC (SCLK, WCLK, DATA and EF) are set to

high-impedance.

7.10.1.2 Loopback external data into onboard DAC

The onboard DAC can also be set to accept serial data

inputs from an external source, e.g. an Electronic Shock

Absorption (ESA) IC. This is known as loopback mode and

is enabled by setting shadow register 7 to 0000. This

enables the serial data output pins (SCLK, WCLK, DATA

and EF) so that data can be routed from the SAA7826 to

an external ESA system (or external DAC).

The serial data from an external ESA IC can then also be

input to the onboard DAC on the SAA7826 by utilising the

serial data input interface (SCLI, SDI and WCLI).

In this mode, a wide range of data formats to the external

ESA IC can be programmed as shown in Table 7.

However, the serial input on the SAA7826 always expects

the input data from the ESA IC to be 16-bit 1fs and the

same data format, either I2S-bus or EIAJ, as the serial

output format (set by decoder register 3).

7.10.2 EXTERNAL DAC INTERFACE

Audio data from the SAA7826 can be sent to an external

DAC, identical to the SAA732x series, in ‘loopback’ mode

(i.e. shadow register 7 is set to 0000).

The SAA7826 is compatible with a wide range of external

DACs. Eleven formats are supported which are given in

Table 7. Figures 14 and 15 show the Philips I

S-bus and

the EIAJ data formats respectively. When the decoder is

operated in lock-to-disc mode, the SCLK frequency

depends on the disc speed factor ‘d’.

All formats are MSB first and 1f

is 44.1 kHz. The polarity

of the WCLK and the data can be inverted; selectable by

decoder register 7. It should be noted that EF is only a

defined output in CD-ROM and 1f

modes.

When using an external DAC (or when using the onboard

DAC in non-loopback mode), the serial data inputs to the

onboard DAC (SCLI, SDI and WCLI) should be tied to

ground.

Table 7 DAC interface formats

Note

1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated

then the first 18 bits contain data.

SAMPLE

FREQUENCY

NUMBER OF

BITS

SCLK (MHz) FORMAT INTERPOLATION

1010 f

16 2.1168 × n CD-ROM

S-bus)

1011 f

16 2.1168 × n CD-ROM (EIAJ) no

1110 f

16/18

(1)

2.1168 × n Philips I

S-bus

16/18 bits

(1)

yes

0010 f

16 2.1168 × n EIAJ 16 bits yes

0110 f

18 2.1168 × n EIAJ 18 bits yes

0000 4f

16 8.4672 × n EIAJ 16 bits yes

0100 4f

18 8.4672 × n EIAJ 18 bits yes

1100 4f

18 8.4672 × n Philips I

S-bus

18 bits

yes

0011 2f

16 4.2336 × n EIAJ 16 bits yes

0111 2f

18 4.2336 × n EIAJ 18 bits yes

1111 2f

18 4.2336 × n Philips I

S-bus

18 bits

yes

SAA7826HL/M1A,557

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SAA7826HL/M1A,557

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