2003 Oct 01 17
Philips Semiconductors Product specification
CD audio decoder, digital servo and filterless
DAC with integrated pre-amp and laser control
SAA7826
W96 1QRSTUVW 1Q
200/n µs
min
11.3/n
µs
11.3/n µs min
90/n µs max
MBG401
Fig.10 Subcode format and timing on pin V4.
Where n = disc speed.
handbook, full pagewidth
CRC flag D0 D1 D2 D3 D126 D127
CDTCLK
CDTRDY
CDTDATA
MBL441
73/n µs to 317/n µs
~1/n ns
200 ns (min)
Fig.11 CD text interface format and timing.
Where n = disc speed.
7.8 FIFO and error correction
The SAA7826 has a ±8 frame FIFO. The error corrector is
a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after de-interleaving by C2, to
help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM). The EF output flags bytes in
error in both audio and CD-ROM modes.
7.8.1 FLAGS OUTPUT (CFLG)
The flags output pin CFLG shows the status of the error
corrector and interpolator and is updated every frame
(7.35 × n kHz). In the SAA7826, 8 × 1-bit flags are present
on the CFLG pin as illustrated in Fig.12. This signal shows
the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by decoder register A.
