2003 Oct 01 15
Philips Semiconductors Product specification
CD audio decoder, digital servo and filterless
DAC with integrated pre-amp and laser control
SAA7826
7.6 Demodulator
7.6.1 FRAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data. The
master counter is only reset if:
• A sync coincidence is detected; sync pattern occurs
588 ±1 EFM clocks after the previous sync pattern
• A new sync pattern is detected within ±6 EFM clocks of
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence is found, and reset LOW if during 61
consecutive frames no sync coincidence is found. The PLL
lock signal can be accessed via the SDA or STATUS pins
selected by decoder registers 2, 7 and new shadow
register C (bank 3).
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 is
pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.6.2 EFM DEMODULATION
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
7.7 Subcode data processing
7.7.1 Q-CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal goes LOW. SUBQREADY-I can be
read via the SDA or STATUS pins, selected via decoder
registers 2, 7 and new shadow register C (bank 3). Good
Q-channel data may be read from pin SDA.
7.7.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
INTERFACE
Data from all the subcode channels (P-to-W) can be read
via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured as
either a 3-wire or 4-wire interface via decoder register F.
The subcode interface output formats are illustrated in
Fig.9, where the RCK signal is supplied by another device
such as a CD graphics decoder.
7.7.3 V4 SUBCODE INTERFACE
Data of subcode channels Q-to-W can be read via pin V4
if selected via decoder register D. The format is similar to
RS232 and is illustrated in Fig.10. The subcode sync word
is formed by a pause of (200/n) µs minimum. Each
subcode byte starts with a logic 1 followed by 7 bits
(Q-to-W). The gap between bytes is variable between
(11.3/n) µs and (90/n) µs.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
7.7.4 CD TEXT INTERFACE
R-to-W subcode data is captured and stored until a
complete CD text PACK is formed. The least significant
16 bits of the PACK are used for a CRC.
The behaviour of the CD text interface is controlled by new
shadow register 7 (bank 2). The interface can either flag
all data (i.e. passed or failed CRC) or it can flag good data
only.
The data ready flag is monitored via pin CDTRDY and is
active LOW. The pulse width varies from 73/n µs, for the
first three packs, to 317/n µs for the fourth pack.
When a PACK becomes available, the initial value of the
CDTDATA pin indicates the CRC result (HIGH = passed;
LOW = failed). The microcontroller can fetch the data by
applying a clock signal (maximum frequency = 5 MHz) to
pin CDTCLK and reading the subsequent bitstream on pin
CDTDATA.
The 128 data bits are streamed out LSB first. A complete
CD text PACK consists of 4 header bytes, 12 data bytes,
and 2 CRC bytes, although the latter 2 bytes are dropped
internally once the CRC calculation is complete. Refer to
the
“Red Book”
for further details relating to the format of a
CD text PACK
The timing diagram for the CD text interface is illustrated in
Fig.11.
