AD9240
REV.
–9–
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily con-
figure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,
V
CORE
= VINA – VINB (1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, V
CORE
, must satisfy the condition,
VREF
V
CORE
VREF
(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, there is an additional limitation placed
on the inputs by the power supply voltages of the AD9240. The
power supplies bound the valid operating range for VINA and
VINB. The condition,
AVSS – 0.3 V < VINA < AVDD + 0.3 V
(3)
AVSS – 0.3 V < VINB < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa-
tions 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9240, see
Table IV.
Refer to Table I and Table II for a summary of the various
analog input and reference configurations.
ANALOG INPUT OPERATION
Figure 24 shows the equivalent analog input of the AD9240
which consists of a differential sample-and-hold amplifier (SHA).
The differential input structure of the SHA is highly flexible,
allowing the devices to be easily configured for either a differen-
tial or single-ended input. The dc offset, or common-mode
voltage, of the input(s) can be set to accommodate either single-
supply or dual supply systems. Note also that the analog inputs,
VINA and VINB, are interchangeable with the exception that
reversing the inputs to the VINA and VINB pins results in a
polarity inversion.
VINA
VINB
C
PIN
+
C
PAR
C
PIN
C
PAR
Q
S1
Q
S1
Q
H1
C
S
C
S
C
H
C
H
Q
S2
Q
S2
Figure 24. Simplified Input Circuit
The input SHA of the AD9240 is optimized to meet the perfor-
mance requirements for some of the most demanding commu-
nication, imaging, and data acquisition applications while
maintaining low power dissipation. Figure 25 is a graph of the
full-power bandwidth of the AD9240, typically 60 MHz. Note
that the small signal bandwidth is the same as the full-power
bandwidth. The settling time response to a full-scale stepped
input is shown in Figure 26 and is typically less than 40 ns to
0.0025%. The low input referred noise of 0.36 LSB’s rms is
displayed via a grounded histogram and is shown in Figure 13.
FREQUENCY – MHz
1
0
–7
1 10 100
–3
–4
–5
–6
–1
–2
–8
–9
–10
AMPLITUDE – dB
Figure 25. Full-Power Bandwidth
SETTLING TIME – ns
CODE
16000
12000
0
0
6010 20 30 40 50
8000
4000
70 80
Figure 26. Settling Time
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two condi-
tions: (1) the common-mode voltage is centered around mid-
supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input
signal voltage span of the SHA is set at its lowest (i.e., 2 V input
span). This is due to the sampling switches, Q
S1
, being CMOS
switches whose R
ON
resistance is very low but has some signal
dependency which causes frequency dependent ac distortion
while the SHA is in the track mode. The R
ON
resistance of a
CMOS switch is typically lowest at its midsupply but increases
symmetrically as the input signal approaches either AVDD or
AVSS. A lower input signal voltage span centered at midsupply
reduces the degree of R
ON
modulation.
B
AD9240
REV.
–10–
Figure 27 compares the AD9240’s THD vs. frequency perfor-
mance for a 2 V input span with a common-mode voltage of
1 V and 2.5 V. Note the difference in the amount of degrada-
tion in THD performance as the input frequency increases.
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be domi-
nated by static nonlinearities such as INL and DNL. It is
important to note that these dc static nonlinearities are inde-
pendent of any R
ON
modulation.
–50
–80
0.1 1 20
–70
–60
–90
10
THD – dB
FREQUENCY – MHz
V
CM
= 1.0V
V
CM
= 2.5V
Figure 27. THD vs. Frequency for V
CM
= 2.5 V and 1.0 V
(A
IN
= –0.5 dB, Input Span = 2.0 V p-p)
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differen-
tial input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancella-
tion of both common-mode distortion and noise. Also, the
required input signal voltage span is reduced a factor of two
which further reduces the degree of R
ON
modulation and its
effects on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 5 V input span) and matched
input impedance for VINA and VINB. Note that only a slight
degradation in dc linearity performance exists between the
2 V and 5 V input span as specified in the AD9240 DC
SPECIFICATIONS.
Referring to Figure 24, the differential SHA is implemented
using a switched-capacitor topology. Hence, its input imped-
ance and its subsequent effects on the input drive source should
be understood to maximize the converter’s performance. The
combination of the pin capacitance, C
PIN
, parasitic capacitance
C
PAR,
and the sampling capacitance, C
S
, is typically less than
16 pF. When the SHA goes into track mode, the input source
must charge or discharge the voltage stored on C
S
to the new
input voltage. This action of charging and discharging C
S
which
is approximately 4 pF, averaged over a period of time and for a
given sampling frequency, F
S
, makes the input impedance ap-
pear to have a benign resistive component (i.e., 83 k at F
S
=
10 MSPS). However, if this action is analyzed within a sam-
pling period (i.e., T = <1/F
S
), the input impedance is dynamic
due to the instantaneous requirement of charging and discharg-
ing C
S
. A series resistor inserted between the input drive source
and the SHA input as shown in Figure 28 provides effective
isolation.
10mF
VINA
VINB
SENSE
AD9240
0.1mF
R
S
*
V
CC
V
EE
R
S
*
VREF
REFCOM
*OPTIONAL SERIES RESISTOR
Figure 28. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several fac-
tors, which include the AD9240 sampling rate, the selected op
amp and the particular application. In most applications, a
30 to 50 resistor is sufficient; however, some applications
may require a larger resistor value to reduce the noise band-
width or possibly limit the fault current in an overvoltage
condition. Other applications may require a larger resistor value
as part of an antialiasing filter. In any case, since the THD
performance is dependent on the series resistance and the above
mentioned factors, optimizing this resistor value for a given
application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance con-
nected to VINA and VINB. The degree of improvement is de-
pendent on the resistor value and the sampling rate. For series
resistor values greater than 100 , the use of a matching resis-
tor is encouraged.
The noise or small-signal bandwidth of the AD9240 is the same
as its full-power bandwidth. For noise sensitive applications, the
excessive bandwidth may be detrimental and the addition of a
series resistor and/or shunt capacitor can help limit the wide-
band noise at the A/D’s input by forming a low-pass filter. Note,
however, that the combination of this series resistance with the
equivalent input capacitance of the AD9240 should be evalu-
ated for those time-domain applications that are sensitive to the
input signal’s absolute settling time. In applications where har-
monic distortion is not a primary concern, the series resistance
may be selected in combination with the SHA’s nominal 16 pF
of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9240, a lower series resistance can be selected to
establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts as a charge reservoir, sinking or sourcing the additional
charge required by the hold capacitor, C
H
, further reducing
current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9240 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response and distor-
tion performance.
B
AD9240
REV.
–11–
Table I. Analog Input Configuration Summary
Input Input Input Range (V) Figure
Connection Coupling Span (V) VINA
1
VINB
1
# Comments
Single-Ended DC 2 0 to 2 1 32, 33 Best for stepped input response applications, suboptimum THD
and noise performance, requires ±5 V op amp.
2 × VREF 0 to VREF 32, 33 Same as above but with improved noise performance due to
2 × VREF increase in dynamic range. Headroom/settling time requirements
of ±5 V op amp should be evaluated.
5 0 to 5 2.5 32, 33 Optimum noise performance, excellent THD performance. Requires
op amp with VCC > +5 V due to insufficient headroom @ 5 V.
2 × VREF 2.5 – VREF 2.5 39 Optimum THD performance with VREF = 1, noise performance
to improves while THD performance degrades as VREF increases
2.5 + VREF to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.
Single-Ended AC 2 or 0 to 1 or 1 or VREF 34 Suboptimum ac performance due to input common-mode level
2 × VREF 0 to 2 × VREF not biased at optimum midsupply level (i.e., 2.5 V).
5 0 to 5 2.5 34 Optimum noise performance, excellent THD performance.
2 × VREF 2.5 – VREF 2.5 35 Flexible input range, Optimum THD performance with VREF = 1.
to Noise performance improves while THD performance degrades as
2.5 + VREF VREF increases to 2.5 V.
Differential AC or 2 2 to 3 3 to 2 29–31 Optimum full-scale THD and SFDR performance well beyond the
DC A/Ds Nyquist frequency.
2 × VREF 2.5 – VREF/2 2.5 + VREF/2 29–31 Same as 2 V to 3 V input range with the exception that full-scale
to to THD and SFDR performance can be traded off for better noise
2.5 + VREF/2 2.5 – VREF/2 performance.
5 1.25 to 3.75 3.75 to 1.25 29–31 Widest dynamic range (i.e., ENOBs) due to optimum noise
performance.
1
VINA and VINB can be interchanged if signal inversion is required.
Table II. Reference Configuration Summary
Reference Input Span (VINA–VINB)
Operating Mode (V p-p) Required VREF (V) Connect To
INTERNAL 2 1 SENSE VREF
INTERNAL 5 2.5 SENSE REFCOM
INTERNAL 2 SPAN 5 AND 1 VREF 2.5 AND R1 VREF AND SENSE
SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM
EXTERNAL 2 SPAN 51 VREF 2.5 SENSE AVDD
(NONDYNAMIC) VREF EXT. REF.
EXTERNAL 2 SPAN 5 CAPT and CAPB SENSE AVDD
(DYNAMIC) Externally Driven VREF REFCOM
EXT. REF. 1 CAPT
EXT. REF. 2 CAPB
B

AD9240ASRL

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Analog to Digital Converters - ADC Complete 14B 10 MSPS Monolithic
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