AC SPECIFICATIONS
Parameter AD9240 Units
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
f
INPUT
= 500 kHz 75.0 dB min
77.5 dB typ
f
INPUT
= 1.0 MHz 77.5 dB typ
f
INPUT
= 5.0 MHz 75.0 dB typ
EFFECTIVE NUMBER OF BITS (ENOB)
f
INPUT
= 500 kHz 12.2 Bits min
12.6 Bits typ
f
INPUT
= 1.0 MHz 12.6 Bits typ
f
INPUT
= 5.0 MHz 12.2 Bits typ
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT
= 500 kHz 76.0 dB min
78.5 dB typ
f
INPUT
= 1.0 MHz 78.5 dB typ
f
INPUT
= 5.0 MHz 78.5 dB typ
TOTAL HARMONIC DISTORTION (THD)
f
INPUT
= 500 kHz –78.0 dB max
–85.0 dB typ
f
INPUT
= 1.0 MHz –85.0 dB typ
f
INPUT
= 5.0 MHz –77.0 dB typ
SPURIOUS FREE DYNAMIC RANGE
f
INPUT
= 500 kHz 90.0 dB typ
f
INPUT
= 1.0 MHz 90.0 dB typ
f
INPUT
= 5.0 MHz 80.0 dB typ
DYNAMIC PERFORMANCE
Full Power Bandwidth 70 MHz typ
Small Signal Bandwidth 70 MHz typ
Aperture Delay 1 ns typ
Aperture Jitter 4 ps rms typ
Acquisition to Full-Scale Step (0.0025%) 45 ns typ
Overvoltage Recovery Time 167 ns typ
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameters Symbol AD9240 Units
CLOCK INPUT
High Level Input Voltage V
IH
+3.5 V min
Low Level Input Voltage V
IL
+1.0 V max
High Level Input Current (V
IN
= DVDD) I
IH
±10 µA max
Low Level Input Current (V
IN
= 0 V) I
IL
±10 µA max
Input Capacitance C
IN
5 pF typ
LOGIC OUTPUTS (with DRVDD = 5 V)
High Level Output Voltage (I
OH
= 50 µA) V
OH
+4.5 V min
High Level Output Voltage (I
OH
= 0.5 mA) V
OH
+2.4 V min
Low Level Output Voltage (I
OL
= 1.6 mA) V
OL
+0.4 V max
Low Level Output Voltage (I
OL
= 50 µA) V
OL
+0.1 V max
Output Capacitance C
OUT
5 pF typ
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50 µA) V
OH
+2.4 V min
Low Level Output Voltage (I
OL
= 50 µA) V
OL
+0.7 V max
Specifications subject to change without notice.
AD9240
REV.
–3–
(AVDD
= +5 V, DVDD= +5 V, DRVDD = +5 V, f
SAMPLE
= 10 MSPS, R
BIAS
= 2 k, VREF = 2.5 V, A
IN
= –0.5 dBFS,
AC Coupled/Differential Input, T
MIN
to T
MAX
unless otherwise noted)
(AVDD
= +5 V, DVDD
= +5 V, T
MIN
to T
MAX
unless otherwise noted)
B
AD9240
REV.
–4–
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter to Min Max Units
AVDD AVSS –0.3 +6.5 V
DVDD DVSS –0.3 +6.5 V
AVSS DVSS –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
DRVSS AVSS –0.3 +0.3 V
REFCOM AVSS –0.3 +0.3 V
CLK AVSS –0.3 AVDD
+ 0.3 V
Digital Outputs DRVSS –0.3 DRVDD
+ 0.3 V
VINA, VINB AVSS –0.3 AVDD
+ 0.3 V
VREF AVSS –0.3 AVDD
+ 0.3 V
SENSE AVSS –0.3 AVDD
+ 0.3 V
CAPB, CAPT AVSS –0.3 AVDD
+ 0.3 V
BIAS AVSS –0.3 AVDD
+ 0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
SWITCHING SPECIFICATIONS
Parameters Symbol AD9240 Units
Clock Period
1
t
C
100 ns min
CLOCK Pulsewidth High t
CH
45 ns min
CLOCK Pulsewidth Low t
CL
45 ns min
Output Delay t
OD
8ns min
13 ns typ
19 ns max
Pipeline Delay (Latency) 3 Clock Cycles
NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
Specifications subject to change without notice.
(T
MIN
to T
MAX
with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, R
BIAS
= 2 k, C
L
= 20 pF)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9240 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
t
CL
t
CH
t
C
t
OD
DATA 1
DATA
OUTPUT
INPUT
CLOCK
ANALOG
INPUT
S1
S2
S3
S4
Figure 1. Timing Diagram
THERMAL CHARACTERISTICS
Thermal Resistance
44-Lead MQFP
θ
JA
= 53.2°C/W
θ
JC
= 19°C/W
PIN CONFIGURATION
3
4
5
6
7
1
2
10
11
8
9
40 39 3841
42
4344 36 35 3437
29
30
31
32
33
27
28
25
26
23
24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9240
12
13
14 15 16 17 18 19 20 21 22
NC = NO CONNECT
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
DVSS
AVSS
DVDD
AVDD
DRVSS
DRVDD
CLK
NC
NC
NC
(LSB) BIT 14
REFCOM
VREF
SENSE
NC
AVSS
AVDD
NC
NC
OTR
BIT 1 (MSB)
BIT 2
NC
NC
NC
CML
NC
CAPT
CAPB
BIAS
NC
VINB
VINA
WARNING!
ESD SENSITIVE DEVICE
B
AD9240
REV.
–5–
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an
overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
T
MIN
or T
MAX
.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, an effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TWO-TONE SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. Two-tone SFDR may be
reported in dBc (i.e., degrades as signal level is lowered), or in
dBFS (always related back to converter full scale).
PIN FUNCTION DESCRIPTIONS
Pin
Number Name Description
1 DVSS Digital Ground
2, 29 AVSS Analog Ground
3 DVDD +5 V Digital Supply
4, 28 AVDD +5 V Analog Supply
5 DRVSS Digital Output Driver Ground
6 DRVDD Digital Output Driver Supply
7 CLK Clock Input Pin
8–10 NC No Connect
11 BIT 14 Least Significant Data Bit (LSB)
12–23 BIT 13–BIT 2 Data Output Bits
24 BIT 1 Most Significant Data Bit (MSB)
25 OTR Out of Range
26, 27, 30 NC No Connect
31 SENSE Reference Select
32 VREF Reference I/O
33 REFCOM Reference Common
34, 38, 40,
43, 44 NC No Connect
35 BIAS* Power/Speed Programming
36 CAPB Noise Reduction Pin
37 CAPT Noise Reduction Pin
39 CML Common-Mode Level (Midsupply)
41 VINA Analog Input Pin (+)
42 VINB Analog Input Pin (–)
*See Speed/Power Programmability section.
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
B

AD9240ASRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Complete 14B 10 MSPS Monolithic
Lifecycle:
New from this manufacturer.
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