AD9240
REV.
–21–
the bandlimited IF signal aliases back into the center of the ADC’s
baseband region (i.e. F
S
/4). At a sample rate of 10 MSPS, an
image of the IF signal centered at 37.5 MHz will be aliased back
to 2.5 MHz which corresponds to one quarter of the sample rate
(i.e. F
S
/4). Note, the IF signal in this case will have undergone a
frequency inversion that may easily be corrected for in the digital
domain.
200V
0.1mF
AD9240
VINA
CML
VINB
50V
AD8009
50V
280V
93.1V
AD8009
200V
22.1V
50V
SAW FILTER
OUTPUT
G
1
= 20dB
G
2
= 12dB
MINI-CIRCUITS
T4-6T
Figure 52. Simplified AD9240 IF Sampling Circuit
To maximize its distortion performance, the AD9240 is config-
ured in the differential mode using a transformer. Preceding the
AD9240 is a bandpass filter and a 32 dB gain stage. A large
gain stage may be required to compensate for the high insertion
losses of a SAW filter used for image rejection. The gain stage
will also provide adequate isolation for the SAW filter from the
transient currents associated with AD9240’s input stage.
The gain stage can be realized using one or two cascaded AD8009
op amps. The AD8009 is a low cost current-feedback op amp
having a third order intercept of 33 dB for a gain of +10 MHz
at 37.5 MHz. A passive bandpass filter is required after the
AD8009 to reduce the resulting second order distortion prod-
ucts and limit its out-of-band noise. The specifications of this
filter are application dependent and will affect both the total
distortion and noise performance of this circuit.
Figure 53 shows the single-tone SNR and SFDR performance of
the AD9240 configured in the 2 V and 5 V span without using
the AD8009 gain stage. Only a slight degradation in SNR perfor-
mance (i.e., 1 dB) was noted with the inclusion of the AD8009
gain stage and a bandpass filter. Note, the tradeoff in SNR and
SFDR (dBFS) performance between the 5 V and 2 V spans at
different signal levels.
INPUT POWER LEVEL – dBFS
40
–30–80 –70 –60 –40
80
60
50
70
30
20
WORST CASE SPURIOUS AND SNR – dBc
10
0
–50 –20 –10 0
SFDR w/5V SPAN
SFDR w/2V SPAN
SNR w/5V SPAN
SNR w/2V SPAN
Figure 53. Single-Tone SNR/SFDR vs. Input Amplitude
@ 37.45 MHz
Figure 54 compares the two tone SFDR performance of the
AD9240 in the 2 V span with and without the use of the AD8009
gain stage. No degradation in distortion performance was noted
with the inclusion of the AD8009 gain stage provided that the
AD8009 2nd order distortion products are sufficiently attenu-
ated by the bandpass filter.
INPUT POWER LEVEL (f
1
= f
2
) – dBFS
40
–90 –30–80 –70 –60 –40
100
90
80
60
50
70
30
20
WORST CASE SPURIOUS – dBc AND dBFS
10
0
–50 –20 –10 0
w/o AD8009 – dBFS
w/AD8009 – dBFS
w/o AD8009 – dBc
w/AD8009 – dBc
85 dB REFERENCE LINE
Figure 54. Two Tone SFDR vs. Input Amplitude
@ f
1
= 36.40 MHz and f
2
= 38.60 MHz
B
AD9240
REV.
–22–
2
3
AD817
V
EE
U3
A
R7
1kV
C16
0.1mF
R8
316V
A
Q1
2N2222
A
C17
10mF
16V
A
C18
0.1mF
R6
820V
+5VA
TP25
R4
50V
JP10
R3
15kV
A
C12
0.1mF
A
R5
10kV
C13
10mF
16V
A
V
IN
V
OUT
GND
REF43
A
EXTERNAL REFERENCE DRIVE
U2
V
CC
C14
0.1mF
6
7
4
V
CC
A
C15
0.1mF
74HC541N
TPD
C19
0.1mF
6
7
2
3
4
V
CC
AD845
A
C21
0.1mF
V
EE
U4
A
R11
500V
C20
0.1mF
A
R14
10kV
A
CW
R13
10kV
BUFFER
JP23
R10
500V
1
2
3
A
B
JP24
DIRECT COUPLE OPTION
C38
AC COUPLE OPTION
JP14
JP13
A
R9
50V
A
J1
VIN
R12
33V
R15
33V
+5VA
A
D2
1N5711
D1
1N5711
AC COUPLE OPTION
+5VA
A
D4
1N5711
D3
1N5711
R39
2
J8
4J8
6
J8
8
J8
10
J8
12
J8
14
J8
16
J8
18
J8
20 J8
22
J8
24 J8
26
J8
39 J8
28 J8
29
J8
30 J8
31
J8
32
J8
34
J8
35 J8
36
J8
37
J8
38
J8
NC
NC
NC
+5VA
U8
DECOUPLING
A
11
10
U8
98
U8
34
U8
1
2
U8
13
12
U8
A
+5VD
U5
DECOUPLING
5
6
U5
12
U5
3
4
U5
SPARE GATES
JP18
JP17
R20
22.1V
13 J8
TP10
R21
22.1V
11
J8
TP11
R22
22.1V
9
J8
TP12
R23
22.1V
7J8
TP13
R24
22.1V
5
J8
TP14
R25
22.1V
3
J8
TP15
R26
22.1V
1
J8
TP16
R27
22.1V
33
J8
TP3
R28
22.1V
27 J8
TP4
R29
22.1V
25 J8
TP5
R30
22.1V
23
J8
TP17
R31
22.1V
21
J8
TP6
R32
22.1V
19 J8
TP7
R33
22.1V
17
J8
TP8
R34
22.1V
15
J8
TP9
C24
0.1mF
+DRVDD
74HC541N
20
A
J9
CLKIN
U5
13 12
U5
98
JP15
CLKB
JP16
CLK
U5
11 10
U8
65
C23
0.1mF
TP2
A
R19
50V
R40
R41
A
R16
5kV
+5VA
R18
5kV
R17
1kV
CW
D13
ADC_CLK
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
+5VD
U6
G1
G2
A7
A6
A5
A4
A3
A2
A1
A0
GND
+DRVDD
20
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
+5VD
U7
G1
G2
A7
A6
A5
A4
A3
A2
A1
A0
GND
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
BIT13
BIT14
OTR
VREF
SENSE
REFCOM
CAPT
CAPB
CML
VINA
VINB
U1
AD9240MQFP
AVDD2
32
31
33
37
36
39
41
42
28
42
29
TP24
C8
0.1mF
A
A
JP7
+5VA
C9
0.1mF
A
25
24 D13
23 D12
22 D11
21 D10
20 D9
19 D8
18 D7
17 D6
16 D5
15 D4
14 D3
13 D2
12 D1
11 D0
5
7
C43
0.1mF
C10
0.1mF
C11
0.1mF
+DRVDD
C2
0.1mF
+
C1
10mF
16V
A
JP6
JP3
+5VA
JP4
JP5
R1
10kV
R2
10kV
A
C41
0.1mF
JP2
TPC
TPD
A
C6
0.1mF
+
C5
10mF
16V
C3
0.1mF
C4
0.1mF
A
CML
A
VINA2
VINA1
JP11
BA
321
VINB2
VINB1
JP12
BA
321
JP8
+5VD
A
DRVSS
DVSS
DRVDD
DVDD
TP1
1
63
CLK
C7
0.1
m
F
AVDD1
AVSS2
AVSS1
ADC_CLK
T1
6
5
4
1
2
3
PRI SEC
R36
200V
A
C36
15pF
R37
33V
R38
33V
VINA1
VINB1
A
C37
15pF
JP21
TPC
JP22
TPD
JP1
CML
R35
50V
A
A
J10
AIN
A
TP26
SJ6
40
J8
AA
+
C28
22mF
25V
C32
0.1mF
L1
TP18
J2+5A
AA
+
C29
22mF
25V
C33
0.1mF
L2
TP19
J3+5D
AA
+
C30
22mF
25V
C34
0.1mF
L3
TP20
J4+V
CC
AA
+
C31
22mF
25V
C35
0.1mF
L4
TP21
J5–V
EE
+
C39
22mF
25V
C40
0.1mF
L5
TP27
J11
+5_OR _+3
+DRVDD
V
EE
V
CC
+5VD
+5VA
J6
TP23
J7
A
JG1-WIRE
ETCH
CKT SIDE
5 SETS OF
PADS TO
CONNECT
GROUNDS
JG1
SJ1
SJ2
SJ3
SJ4
SJ5
AGND
DGND
TP22
VINA2
VINB2
TPD
TPC
74HC14
74HC04
D7 9
D8 8
D9 7
D10 6
D11 5
D12 4
D13 3
2
10
19
1
11
12
13
14
15
16
17
18
11
12
13
14
15
16
17
18
CLK 9
D0 8
D1 7
D2 6
D3 5
D4 4
D5 3
10
19
1
C25
0.1mF
C22
0.1mF
C26
0.1mF
C42
0.1mF
BIAS
35
R
BIAS
D6 2
Figure 55. Evaluation Board Schematic
B
AD9240
REV.
–23–
Figure 56. Evaluation Board Component Side Layout
(Not to Scale)
Figure 57. Evaluation Board Solder Side Layout
(Not to Scale)
Figure 58. Evaluation Board Ground Plane Layout
(Not to Scale)
Figure 59. Evaluation Board Power Plane Layout
(Not to Scale)
B

AD9240ASRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Complete 14B 10 MSPS Monolithic
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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