AD9240
REV.
–8–
CLOCK FREQUENCY – MHz
SINAD – dB
80
20
12010
70
60
50
40
30
10
0
R
BIAS
= 10kV
R
BIAS
= 20kV
R
BIAS
= 200kV
R
BIAS
=
4kV
R
BIAS
=
2kV
Figure 21. SINAD vs. Clock Frequency for Varying R
BIAS
Values (V
CM
= 2.5 V, A
IN
= –0.5 dB, 5 V Span, f
IN
= f
CLK
/2)
CLOCK FREQUENCY – MHz
POWER – mW
400
100
2204 6 8 10 12 14 16 18
350
300
250
200
150
R
BIAS
= 1.7kV
R
BIAS
= 2kV
R
BIAS
= 2.5kV
R
BIAS
= 3.3kV
R
BIAS
= 5kV
R
BIAS
= 10kV
R
BIAS
= 100kV
Figure 22. Power Dissipation vs. Clock Frequency for
Varying R
BIAS
Values
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 23, a simplified model of the AD9240, highlights the rela-
tionship between the analog inputs, VINA, VINB, and the ref-
erence voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF defines
the maximum input voltage to the A/D core. The minimum input
voltage to the A/D core is automatically defined to be –VREF.
V
CORE
VINA
VINB
+VREF
–VREF
A/D
CORE
14
AD9240
Figure 23. Equivalent Functional Input Circuit
INTRODUCTION
The AD9240 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D con-
nected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the differ-
ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash er-
rors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be con-
figured to interface with +5 V or +3.3 V logic families.
The AD9240 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value, and should be minimized.
Speed/Power Programmability
The AD9240’s maximum conversion rate and associated power
dissipation can be set using the part’s BIAS pin. A simplified
diagram of the on-chip circuitry associated with the BIAS pin is
shown in Figure 20.
AD9240
BIAS
R
BIAS
I
FIXED
ADC
BIAS
Figure 20.
The value of R
BIAS
can be varied over a limited range to set the
maximum sample rate and power dissipation of the AD9240. A
typical plot of S/(N+D) @ f
IN
= Nyquist vs. f
CLK
at varying
R
BIAS
is shown in Figure 21. A similar plot of power vs. f
CLK
at varying R
BIAS
is shown in Figure 22. These plots indicate
typical performance vs. R
BIAS
. Note that all other plots and
specifications in this data sheet reflect performance at a fixed
R
BIAS
= 2 kΩ.
