XE3005I033TRLF Datasheet XE3005I033TRLF, XE3005I064TRLF | P13-P15

XE3005/XE3006

3 SERIAL COMMUNICATIONS

3.1 SERIAL AUDIO INTERFACE

The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. The 4 terminals are listed

below:

• BCLK: Bit serial clock, one clock cycle corresponds to one data bit transmitted or received.

• FSYNC: Frame Synchronization. This signal indicates the start of a data word. The frequency of the FSYNC

corresponds to the sample frequency of the CODEC.

• SDI: Serial Data In, data received from external device and sent to DAC.

• SDO: Serial Data Out, data received from ADC and sent to external device.

The same clock (BCLK) and synchronization (FSYNC) signals are used for both sending and receiving. The

synchronization signal FSYNC must have a fixed ratio with the master clock signal MCLK.

The Serial Audio Interface supports two formats that are commonly used for audio/voice CODECs and that are referred to

as SFS (Short Frame Synchronization) and LFS (Long Frame Synchronization). Data can be transmitted and received in

2 channels. Which channel is selected depends on the programmed values in the registers. The two interface protocols

are shown below.

FSYNC

SDO

SDI

BCLK

msb

lsb

msb

channel 1, sample n

channel 2, no data channel 1, sample n+1

n+1

Figure 13: Audio interface timing LFS mode, channel 1

FSYNC

BCLK

channel 1, sample n channel 2, sample n

channel 1, sample n+1

SDO

SDI

msb

lsb

msb

n+1

Figure 14: Audio interface timing in SFS mode, channel 1

XE3005/XE3006

SDI Data should be changed on the rising edge of BCLK. The SDI data will be read by the CODEC on the falling edge of

BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling edge of the

BLCK. Each rising edge of the FSYNC indicates the start of a new sample.

3.1.1 LFS Optimization

For transmitting and receiving, 32 clock cycles in one frame are always required (figure 12 and 13). This is even the case

when only 16 bits have to be sent or received. In most cases this can be handled easily with a DSP and microcontroller.

If the user wants to send a minimum of BLCK cycles, it is possible to shorten channel 1 (channel 2 can not be shortened).

In the LFS mode the possibility exists to shorten the number of BLCK cycles to 17 instead of 32. In this case the data is

transmitted and received in channel 2. Channel 1 is shortened to one BLCK cycle only.

Note! This optimization is possible in slave mode only.

The figure 15 shows this special LFS mode.

Figure 15: Audio interface timing in LFS mode, 17 BLCK cycles, channel 2

3.2 REGISTER PROGRAMMING

The control registers define the configuration of the CODEC and define the various modes of operation. During power-up,

all registers will be configured with default values. The control register set consists of 16 registers. A detailed description

is provided chapter 7.

The control registers can be changed in the two following ways:

1. Logic values at SPI pins during power-up

There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and MOSI

during the power up startup sequence as described in section 2.1.10

Value at power up Influenced bits of registers comments

SS = 1

SS = 0

MCLKDIV division by 1

MCLKDIV division by 2

SCK = 0

SCK = 1

SFS protocol

LFS protocol

MOSI = 0

MOSI = 1

preamplifier gain x5

preamplifier gain x20

FSYNC

SDO

SDI

BCLK

msb

lsb

channel 1, no data

channel 2, sample n

msb

channel 2, sample n+1

channel 1, no data

XE3005/XE3006

Using the SPI pins at startup the user is able to configure the CODEC in the corresponding setups without

reprogramming through the SPI interface and protocol. In best case the SPI interface can then be completely omitted and

the 3 SPI pins can be fixed to ‘0’ or ‘1’.

2. Programming through SPI interface after power-up

Once the device has been powered up, the configuration registers can be modified at all times (also when the device is

active) through the SPI interface.

The following section describes the SPI protocol which is required to change the control registers from their default

values.

3.3 SERIAL PERIPHERAL INTERFACE - SPI

The serial peripheral interface (SPI) allows the device to communicate synchronously with other devices such as a

microprocessor or a DSP. The CODEC interface only implements a slave controller. This section describes the

communication from master (e.g. DSP) to slave (CODEC pin MOSI) and from slave (CODEC pin MISO) to a master (e.g.

DSP).

Four lines are used to transmit data between the slave and master:

- MOSI (Master Out, Slave In) data from master to slave, synchronous with the SPI clock (SCK).

- MISO (Master In, Slave Out) data from slave to master, synchronous with the SPI clock (SCK).

- SCK (Serial Clock) synchronizes the data bits of MOSI and MISO.

- SS (Slave Select) Slave devices are selected by activating SS.

3.3.1 Protocol

During SPI communication, data is simultaneously transmitted and received.

0 1 15

SCK

MOSI

MISO

15 0

disable

1/F

sck

recovery

…

Figure 16: SPI signal timing

The master puts data on the MOSI line on the falling edge of SCK; the slave reads the data on the rising edge of SCK.

The slave puts data on the MISO line on the falling edge of SCK; the master reads the data on the rising edge of SCK.

Transmission in either direction is by 2 bytes with MSB first.

The SS pin should be kept low during the whole transfer of data.

There are three timing constraints:

- Recovery time (t

recovery

) between the falling edge of SS and the falling edge of SCK.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

XE3005I033TRLF

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IC CODEC LOW PWR 16BIT 20-TSSOP

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