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XE3005/XE3006
2.1.3 DAC Signal Channel
The DAC is based on a multi bit sigma-delta modulator, which operates at a frequency of 8 times the sampling rate. The
outputs of the modulator are 2’s complement words of 6 bit. A pulse-width modulator (PWM) converts the 6 bit words into
2 single bit streams at 256 times the sampling frequency. Finally the 2 bit streams are supplied to the power amplifier.
The Power Amplifier is a Class D amplifier, which offers higher efficiency than the traditional Class AB topologies. It uses
a three-state unbalanced PWM. This means that both channels of the PA (AOUTP and AOUTN) will not switch at the
same time, therefore the outputs are not purely differential (see figure 5 and 6)
From Serial Audio
Interface
P
N
bit streams
@ 256xFsync
Interpolator
&
Modulator
dac_in(15:0)
@ Fsync
pwm_in(5:0)
@ 8xFsync
Power
Amplifier
s
s = 1
s = 0
P
N
P
N
VSSPA
VDDPA
Pulse Width
Modulator
AOUTP
AOUTN
XE3005/6
Figure 6: DAC block diagram
Figure 6 shows the relation of input and output samples of the PWM (The timing diagram is not to scale in the time-axis).
pwm_in(5:0) = -1
P
N
OUTP-OUTN
1/(256 x Fsync) 2/(256 x Fsync)
pwm_in(5:0) = 1 pwm_in(5:0) = 0 pwm_in(5:0) = 2
1/(8 x Fsync)
1
0
1
0
VDDPA
VSSPA
-VDDPA
1/(256 x Fsync)
Figure 7: Examples PWM in and out (not to scale)
The DAC receives 16-bit wide 2’s complement format through the Serial Audio Interface. The protocol can be selected
through register J. The complete DAC and PA amplifier chain can be powered-down through register I.
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XE3005/XE3006
2.1.4 Digital Loop Back
In digital loop back mode, the ADC output is routed directly to the DAC input. This allows in-circuit system level tests. The
digital loop back mode can be selected through register J.
2.1.5 Operating Frequency
A master clock (MCLK) has to be applied to the XE3005/3006. The clock frequency of the signal applied to the MCLK pin
may vary between 1.024 MHz minimum and 33.9 MHz maximum. The maximum internal clock signal frequency
(MCLK/div_factor) should not exceed 12.288 MHz.
The div_factor can be set by the user in register I to 1,2 or 4. The default value for div_factor is ‘1’.
2.1.6 Serial Audio Interface
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. It operates on the bit serial
clock BCLK and the frame synchronization signal FSYNC. The sampling frequency of the CODEC corresponds to the
rate at which the Audio Serial Interface will put out succeeding frames. One frame always corresponds to one sample.
One frame always contains 2 channels.
Synchronizing the Serial Audio Interface to the MCLK is recommended. FSYNC and MCLK must have a fixed ratio as
defined by the following relation:
FSYNC = Sampling frequency = frame rate = MCLK/(256 x div_factor).
The pin BCLK defines the time when the data must be presented to the serial audio interface and shifted into (pin SDI) or
out of (pin SDO) the CODEC. The number of BCLK periods in one FSYNC period is 32. The user can select to use the
first 16 clock cycles (channel 1) or the second 16 clock cycles (channel 2) of BLCK to shift in or out the data samples.
The table below shows some examples of the relationships between MCLK, BCLK and FSYNC
MCLK Div_factor BCLK FSYNC
2048 kHz 1 256 kHz 8 kHz
8192 kHz 4 256 kHz 8 kHz
5120 kHz 1 640 kHz 20 kHz
22579.2 kHz 2 1411.2 kHz 44.1 kHz
The table below shows the possible functional configurations of the serial audio interface
CODEC supported protocol
master LFS (Long Frame Sync)
slave LFS, LFS Optimization and SFS (Short Frame Sync)
By default the Serial Audio Interface operates in slave, SFS mode. In slave mode the user needs to generate the signals
BLCK, FSYNC and supply to the CODEC.
In master mode the CODEC generates the BLCK and FSYNC signals. In that case the BLCK operates at 32 times the
frequency of FSYNC. The CODEC master mode can be used with the LFS protocol only.
The register J is used for the different setups of the serial audio interface.
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XE3005/XE3006
2.1.7 Serial Peripheral Interface - SPI
The SPI interface is used to control register values. It is a serial communications interface that is independent of the rest
of the CODEC. It allows the device to communicate synchronously with a microprocessor or DSP. The CODEC interface
only implements a slave controller.
A detailed description can be found in chapter 3.3.
2.1.8 Sandman™ ADC Function
The Sandman™ function monitors the signals, which are processed in the ADC signal channel and the DAC signal
channel. The logic output signal SMAD indicates whether the ADC signal channel has processed an audio signal or only
noise, and for how long. The reference signal amplitude can be selected through register O, the time window parameters
are the off time and on time (registers L, M and N).
Amp.
Σ∆
modulator
Decimator
Serial Audio
Interface
BCLK
FSYNC
SDO
AIN
Sandman
Interface
SMAD
Figure 8: Implementation of the Sandman function for the ADC (SMAD)
The logic output SMAD can be used to power-down or reduce clock speed in other devices in the application, such as a
microcontroller, DSP or wireless link. Also, SMAD can be used as phone pick-up indicator. The Sandman™ function is
illustrated in Figure 9 and is valid for both SMAD (related to the ADC signal) and SMDA (related to the DAC signal).
Initially, SMAD is inactive (low), which means that “noise” is processed by the ADC, i.e. no audio signal amplitude above
the Reference. The Sandman™ Interface compares every output sample of the ADC signal channel to the Reference
value. If the signal is lower than the Reference value, SMAD remains inactive (low).
As soon as the signal passes the reference (time = 1), the on-time counter is started. (for the moment defined by time=’x’
see Figure 9). However, as the signal returns below the reference (time = 2) before the on-time counter has reached the
on time, the on-time counter is reset and the SMAD signal remains inactive (low).
The next time the signal gets higher than the Reference (time = 3), the on-time counter is started again and when it
reaches the on time, the SMAD signal becomes active (high), indicating that an audio signal is present (time = 4). As long
as the signal remains above the Reference, nothing happens and the SMAD signal remains active (high). When the
signal falls below the Reference (time = 5), the off-time counter is started, but as it does not reach the off time before the
signal passes again the Reference (time = 6), SMAD remains active (high). Also during the period from time = 7 to time =
8, the off time counter does not reach the off time.
When the signal falls below the Reference (time = 9) and remains below the Reference until the off-time counter has
reached the off-time, the SMAD signal is changed into the inactive (low) state (time = 10).

XE3005I033TRLF

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IC CODEC LOW PWR 16BIT 20-TSSOP
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