© Semtech 2005 www.semtech.com
23
XE3005/XE3006
5.3.6 Timing Requirements of serial audio interface
Ref.
No. *
Characteristics
Test
Conditions
Min Typ Max Unit
1 Master Clock Frequency for MCLK = 1/ T
1024 5.12 33 MHz
1
MCLK Duty Cycle
45 55 %
2
Rise Time for All Digital Signals
10 ns
3
Fall Time for All Digital Signals
10 ns
4
Hold time BCLK or FSYNC high after MCLK low
T/4 ns
5
Setup time BCLK or FSYNC high to MCLK low
T/4 ns
6
Hold time BCLK or FSYNC low after MCLK low
C
Load
= 10pF
T/4 ns
7
Setup time BCLK or FSYNC low to MCLK low
T/4 ns
8 Bit Clock Frequency for BCLK = 1 / TBCLK
32xFSYNC
MCLK/2
MHz
9
Setup time data input SDI to BCLK low
T
BCLK/4 ns
10
Hold time data input SDI after BCLK low
T
BCLK/4 ns
11
Delay time SDO valid after BCLK high
T
BCLK/4 ns
12
Setup time data input FSYNC to BCLK low
T
BCLK/4 ns
13
Hold time data input FSYNC after BCLK low
T
BCLK/4 ns
*see figure 18,19 for LFS and 20, 21 for SFS
