PIC18FXX20
DS39583C-page 16 2010 Microchip Technology Inc.
3.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADR:EEADRH with the desired memory
location, EEDATA with the data to be written, and
initiating a memory write by appropriately configuring
the EECON1 and EECON2 registers. A byte write
automatically erases the location and writes the new
data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit be set only when absolutely
necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The write begins on the falling edge of the 4th SCLK
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-8: PROGRAM DATA FLOW
FIGURE 3-9: DATA EEPROM WRITE TIMING
Start
Start Write
Set Data
Done
No
Yes
Done
?
Enable Write
Unlock Sequence
55h - EECON2
AAh - EECON2
Sequence
Set Address
WR bit
Clear ?
No
Yes
n
SCLK
SDATA
SDATA = Input
0000
BSF EECON1, WR
4-bit Command
1234
1
21516
P5
P5A
P10
12
n
Poll WR bit, Repeat Until Clear
16-bit Data
Payload
1234
1
21516
123
P5
P5A
4
1 2 15 16
P5 P5A
0000
MOVF EECON1, W, 0
4-bit Command
0000
4-bit Command
Shift Out Data
MOVWF TABLAT
SCLK
SDATA
(see below)
(see Figure 4-6)
SDATA = Input SDATA = Output
Poll WR bit
