2010 Microchip Technology Inc. DS39583C-page 7
PIC18FXX20
3.0 DEVICE PROGRAMMING
3.1 High Voltage ICSP Bulk Erase
Erasing Code or Data EEPROM is accomplished by
writing an “erase option” to address 3C0004h. Code
memory may be erased portions at a time, or the user
may erase the entire device in one action. “Bulk Erase”
operations will also clear any code protect settings
associated with the memory block erased. Erase
options are detailed in Table 3-1.
TABLE 3-1: BULK ERASE OPTIONS
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th SCLK after the NOP command), serial execution
will cease until the erase completes (parameter P11).
During this time, SCLK may continue to toggle, but
SDATA must be held low.
The code sequence to erase the entire device is shown
in Figure 3-1 and the flowchart is shown in Figure 3-2.
FIGURE 3-1: BULK ERASE COMMAND
SEQUENCE
FIGURE 3-2: BULK ERASE FLOW
FIGURE 3-3: BULK ERASE TIMING
Description Data
Chip Erase 80h
Erase Data EEPROM 81h
Erase Boot Block 83h
Erase Block 1 88h
Erase Block 2 89h
Erase Block 3 8Ah
Erase Block 4 8Bh
Erase Block 5 8Ch
Erase Block 6 8Dh
Erase Block 7 8Eh
Erase Block 8 8Fh
Note: A bulk erase is the only way to reprogram
code protect bits from an on-state to an
off-state.
Non-code protect bits are not returned to
default settings by a bulk erase. These bits
should be programmed to ones, as out-
lined in Section 3.6, "Configuration Bits
Programming".
4-Bit
Command
Data
Payload
Core Instruction
0000
0000
0000
0000
0000
0000
1100
0000
0000
0E 3C
6E F8
0E 00
6E F7
0E 04
6E F6
00 80
00 00
00 00
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 80h TO 3C0004h to
erase entire device.
NOP
Hold SDATA low until
erase completes.
Start
Done
Write 80h
To Erase
Entire Device
Load Address
Pointer to
3C0004h
Delay P11+P10
Time
n
1234
1
21516
123
SCLK
P5
P5A
SDATA
SDATA = Input
00011
P11
P10
Erase Time
00 0 000 0 0
12
00
4
0
12 1516
P5
123
P5A
4
0000
n
4-bit Command
4-bit Command
4-bit Command
16-bit
Data Payload
16-bit
Data Payload
16-bit
Data Payload
PIC18FXX20
DS39583C-page 8 2010 Microchip Technology Inc.
3.1.1 LOW VOLTAGE ICSP BULK ERASE
When using low voltage ICSP, the part must be
supplied by the voltage specified in parameter #D111,
if a bulk erase is to be executed. All other bulk erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the bulk erase
limit, refer to the erase methodology described in
Sections 3.1.2 and 3.2.2.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the bulk erase
limit, follow the methodology described in Section 3.3
and write ones to the array.
3.1.2 ICSP MULTI-PANEL SINGLE ROW
ERASE
Irrespective of whether high or low voltage ICSP is
used, it is possible to erase single row (64 bytes of
data) in all panels at once. For example, in the case of
a 64-Kbyte device (8 panels), 512 bytes through 64
bytes in each panel can be erased simultaneously dur-
ing each erase sequence. In this case, the offset of the
erase within each panel is the same (see Figure 3-6).
Multi-panel single row erase is enabled by appropri-
ately configuring the Programming Control register
located at 3C0006h.
The multi-panel single row erase duration is externally
timed and is controlled by SCLK. After a “Start Pro-
gramming” command is issued (4-bit, ‘1111’), a NOP is
issued, where the 4th SCLK is held high for the
duration of the programming time, P9.
After SCLK is brought low, the programming sequence
is terminated. SCLK must be held low for the time spec-
ified by parameter P10 to allow high voltage discharge
of the memory array.
The code sequence to program a PIC18FXX20 device
is shown in Table 3-2. The flowchart shown in
Figure 3-4 depicts the logic necessary to completely
erase a PIC18FXX20 device. The timing diagram that
details the “Start Programming” command, and
parameters P9 and P10 is shown in Figure 3-7.
Note: The TBLPTR register must contain the
same offset value when initiating the pro-
gramming sequence as it did when the
write buffers were loaded.
2010 Microchip Technology Inc. DS39583C-page 9
PIC18FXX20
TABLE 3-2: ERASE CODE MEMORY CODE SEQUENCE
FIGURE 3-4: MULTI-PANEL SINGLE ROW ERASE CODE MEMORY FLOW
4-Bit
Command
Data Payload Core Instruction
Step 1: Direct access to config memory.
0000
0000
0000
8E A6
8C A6
86 A6
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
Step 2: Configure device for multi-panel writes.
0000
0000
0000
0000
0000
0000
1100
0E 3C
6E F8
0E 00
6E F7
0E 06
6E F6
00 40
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 06h
MOVWF TBLPTRL
Write 40h to 3C0006h to enable multi-panel erase.
Step 3: Direct access to code memory and enable erase.
0000
0000
0000
0000
0000
0000
8E A6
9C A6
88 A6
6A F8
6A F7
6A F6
BSF EECON1, EEPGD
BCF EECON1, CFGS
BSF EECON1, FREE
CLRF TBLPTRU
CLRF TBLPTRH
CLRF TBLPTRL
Step 4: Erase single row of all panels at an offset.
1111
0000
<DummyLSB>
<DummyMSB>
00 00
Write 2 dummy bytes and start programming.
NOP - hold SCLK high for time P9.
Step 5: Repeat step 4, with Address Pointer incremented by 64 until all panels are erased.
Done
Start
Delay P9 + P10
Time for Erase
to occur
All
Panels
Done?
No
Yes
Addr = 0
Configure
Device for
Multi-Panel Erase
Addr = Addr + 64
Start Erase Sequence
and hold SCLK High
Until Done

PIC18F8620-I/PT

Mfr. #:
Manufacturer:
Microchip Technology
Description:
8-bit Microcontrollers - MCU 64KB 3840 RAM 68I/O
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