PIC18FXX20
DS39583C-page 4 2010 Microchip Technology Inc.
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through Table Reads and Table
Writes. Their locations in the memory map are shown
in Figure 2-3.
Users may store identification information (ID) in eight
ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the Configuration bits. These bits select various device
options, and are described in Section 5.0. These
Configuration bits read out normally, even after code
protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
Device ID bits. These bits may be used by the
programmer to identify what device type is being
programmed, and are described in Section 5.0. These
Device ID bits read out normally, even after code
protection.
2.3.1 MEMORY ADDRESS POINTER
Memory in the address space 0000000h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointer registers:
TBLPTRU, at RAM address 0FF8h
TBLPTRH, at RAM address 0FF7h
TBLPTRL, at RAM address 0FF6h
The 4-bit command, ‘0000’ (Core Instruction), is used
to load the Table Pointer prior to using many Read or
Write operations.
FIGURE 2-3: CONFIGURATION AND ID LOCATIONS FOR PIC18FXX20 DEVICES
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]
ID Location 1 200000h
ID Location 2 200001h
ID Location 3 200002h
ID Location 4 200003h
ID Location 5 200004h
ID Location 6 200005h
ID Location 7 200006h
ID Location 8 200007h
CONFIG1L 300000h
CONFIG1H 300001h
CONFIG2L 300002h
CONFIG2H 300003h
CONFIG3L 300004h
CONFIG3H 300005h
CONFIG4L 300006h
CONFIG4H 300007h
CONFIG5L 300008h
CONFIG5H 300009h
CONFIG6L 30000Ah
CONFIG6H 30000Bh
CONFIG7L 30000Ch
CONFIG7H 30000Dh
Device ID1 3FFFFEh
Device ID2 3FFFFFh
Note: Sizes of memory areas are not to scale.
000000h
1FFFFFh
3FFFFFh
01FFFFh
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
2FFFFFh
2010 Microchip Technology Inc. DS39583C-page 5
PIC18FXX20
2.4 High Level Overview of the
Programming Process
Figure 2-4 shows the high level overview of the
programming process. First, a bulk erase is performed.
Next, the Code Memory, ID Locations, and Data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
2.5 Entering High Voltage ICSP
Program/Verify Mode
The high voltage ICSP Program/Verify mode is entered
by holding SCLK and SDATA low and then raising
MCLR/VPP to VIHH (high voltage). Once in this mode,
the Code Memory, Data EEPROM, ID Locations, and
Configuration bits can be accessed and programmed in
serial fashion.
The sequence that enters the device into the
Program/Verify mode places all unused I/Os in the high
impedance state.
2.5.1 ENTERING LOW VOLTAGE ICSP
PROGRAM/VERIFY MODE
When the LVP configuration bit is ‘1’ (see Section 5.3),
the low voltage ICSP mode is enabled. Low voltage
ICSP Program/Verify mode is entered by holding SCLK
and SDATA low, placing a logic high on PGM, and then
raising MCLR
/VPP to VIH. In this mode, the RB5/PGM
pin is dedicated to the programming function and
ceases to be a general purpose I/O pin.
The sequence that enters the device into the
Program/Verify mode, places all unused I/Os in the
high impedance state.
FIGURE 2-5: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
FIGURE 2-4: HIGH LEVEL
PROGRAMMING FLOW
FIGURE 2-6: ENTERING LOW
VOLTAGE PROGRAM/
VERIFY MODE
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
VDD
D110
P13
P1
Start
Program Memory
Program IDs
Program Data
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
MCLR/VPP
P12
SDATA
SDATA = Input
SCLK
PGM
P15
VDD
VIH
VIH
PIC18FXX20
DS39583C-page 6 2010 Microchip Technology Inc.
2.6 Serial Program/Verify Operation
The SCLK pin is used as a clock input pin and the
SDATA pin is used for entering command bits and data
input/output during serial operation. Commands and
data are transmitted on the rising edge of SCLK,
latched on the falling edge of SCLK, and are Least
Significant bit (LSb) first.
2.6.1 4-BIT COMMANDS
All instructions are 20-bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, SCLK is cycled four times. The commands
needed for programming and verification are shown in
Table 2-3.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data, or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Figure 2-4. The 4-bit
command is shown MSb first. The command operand,
or “Data Payload”, is shown <MSB><LSB>. Figure 2-7
demonstrates how to serially present a 20-bit
command/operand to the device.
2.6.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to setup
registers as appropriate for use with other commands.
TABLE 2-3: COMMANDS FOR
PROGRAMMING
TABLE 2-4: SAMPLE COMMAND
SEQUENCE
FIGURE 2-7: TABLE WRITE, POST-INCREMENT TIMING (1101)
Description
4-Bit
Command
Core Instruction
(Shift in16-bit instruction)
0000
Shift out TABLAT register 0010
Table Read 1000
Table Read, post-increment 1001
Table Read, post-decrement 1010
Table Read, pre-increment 1011
Table Write 1100
Table Write, post-increment by 2 1101
Table Write, post-decrement by 2 1110
Table Write, start programming 1111
4-Bit
Command
Data
Payload
Core Instruction
1101 3C 40 Table Write,
post-increment by 2
1234
SCLK
P5
SDATA
SDATA = Input
5678 1
234
P5A
9
10 11 13 15 161412
Fetch Next 4-bit Command
1011
1234
nnnn
P3
P2
P2A
000000 010001111 0
04C3
P4
4-bit Command 16-bit Data Payload
P2B

PIC18F8620-I/PT

Mfr. #:
Manufacturer:
Microchip Technology
Description:
8-bit Microcontrollers - MCU 64KB 3840 RAM 68I/O
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New from this manufacturer.
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