PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 10 of 52
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
8.2.1.3 Software reset
A reset is automatically generated at power-on. A reset can also be initiated with the
software reset command. Software reset command means setting bits 6, 4, and 3 in
register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence
01011000 (58h), see Figure 6
.
In reset state all registers are set according to Table 8 and the address pointer returns to
address 00h.
The PCF85063TP resets to:
Time — 00:00:00
Date — 20000101
WeekdaySaturday
Fig 6. Software reset command
V
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36
6'$
6&/
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Table 8. Register reset values
Address Register name Bit
7 6 5 4 3 2 1 0
00h Control_1 00000000
01h Control_2 00000000
02h Offset 00000000
03h RAM_byte 00000000
04h Seconds 10000000
05h Minutes 00000000
06h Hours 00000000
07h Days 00000001
08h Weekdays 00000110
09h Months 00000001
0AhYears 00000000
PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 11 of 52
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
8.2.2 Register Control_2
[1] Default value.
8.2.2.1 MI and HMI: minute and half minute interrupt
The minute interrupt (bit MI) and half minute interrupt (bit HMI) are pre-defined timers for
generating interrupt pulses on pin INT
; see Figure 7. The timers are running in sync with
the seconds counter (see Table 19 on page 17
).
The minute and half minute interrupts must only be used when the frequency offset is set
to normal mode (MODE = 0), see Section 8.2.3
. In normal mode, the interrupt pulses on
pin INT
are
1
64
s wide.
When starting MI, the first interrupt will be generated after 1 second to 59 seconds. When
starting HMI, the first interrupt will be generated after 1 second to 29 seconds.
Subsequent periods do not have such a delay. The timers can be enabled independently
from one another. However, a minute interrupt enabled on top of a half minute interrupt is
not distinguishable.
Table 9. Control_2 - control and status register 2 (address 01h) bit description
Bit Symbol Value Description
7 to 6 - 00 unused
5MI minute interrupt
0
[1]
disabled
1 enabled
4HMI half minute interrupt
0
[1]
disabled
1 enabled
3TF timer flag
0
[1]
no timer interrupt generated
1 flag set when timer interrupt generated
2 to 0 COF[2:0] see Table 11
CLKOUT control
In this example, the TF flag is not cleared after an interrupt.
Fig 7. INT example for MI
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PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 12 of 52
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
The duration of the timer is affected by the register Offset (see Section 8.2.3). Only when
OFFSET[6:0] has the value 00h the periods are consistent.
8.2.2.2 TF: timer flag
The timer flag (bit TF) is set logic 1 on the first trigger of MI or HMI and remains set until it
is cleared by command.
8.2.2.3 COF[2:0]: Clock output frequency
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
COF[2:0] bits in the register Control_2. Frequencies of 32.768 kHz (default) down to 1 Hz
can be generated for use as a system clock, microcontroller clock, input to a charge
pump, or for calibration of the oscillator.
Pin CLKOUT is a push-pull output and enabled at power-on. CLKOUT can be disabled by
setting COF[2:0] to 111. When disabled, the CLKOUT is LOW.
The duty cycle of the selected clock is not controlled but due to the nature of the clock
generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.
The STOP bit function can also affect the CLKOUT signal, depending on the selected
frequency. When the STOP bit is set logic 1, the CLKOUT pin generates a continuous
LOW for those frequencies that can be stopped. For more details of the STOP bit function,
see Section 8.2.1.2
.
[1] Duty cycle definition: % HIGH-level time : % LOW-level time.
[2] Default value.
[3] 1 Hz clock pulses are affected by offset correction pulses.
Table 10. Effect of bits MI and HMI on INT generation
Minute interrupt (bit MI) Half minute interrupt (bit HMI) Result
0 0 no interrupt generated
1 0 an interrupt every minute
0 1 an interrupt every 30 s
1 1 an interrupt every 30 s
Table 11. CLKOUT frequency selection
COF[2:0] CLKOUT frequency (Hz) Typical duty cycle
[1]
Effect of STOP bit
000
[2]
32768 60 : 40 to 40 : 60 no effect
001 16384 50 : 50 no effect
010 8192 50 : 50 no effect
011 4096 50 : 50 CLKOUT = LOW
100 2048 50 : 50 CLKOUT = LOW
101 1024 50 : 50 CLKOUT = LOW
110 1
[3]
50 : 50 CLKOUT = LOW
111 CLKOUT = LOW - -

PCF85063TP/1Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Real Time Clock Low Power Real time clocks
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