PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 34 of 52
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
[1] A detailed description of the I
2
C-bus specification is given in Ref. 12 “UM10204.
[2] I
2
C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
IH(min)
of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
[4] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
f
.
Table 32. I
2
C-bus characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +85
C; f
osc
= 32.768 kHz; quartz R
s
=60k
; C
L
= 7 pF; unless otherwise
specified. All timing values are valid within the operating supply voltage and temperature range and referenced to V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
[1]
.
Symbol Parameter Conditions Min Max Unit
C
b
capacitive load for
each bus line
- 400 pF
f
SCL
SCL clock frequency
[2]
0 400 kHz
t
HD;STA
hold time (repeated)
START condition
0.6 - s
t
SU;STA
set-up time for a
repeated START
condition
0.6 - s
t
LOW
LOW period of the
SCL clock
1.3 - s
t
HIGH
HIGH period of the
SCL clock
0.6 - s
t
r
rise time of both SDA
and SCL signals
20 300 ns
t
f
fall time of both SDA
and SCL signals
[3][4]
20 (V
DD
/5.5V) 300 ns
t
BUF
bus free time between
a STOP and START
condition
1.3 - s
t
SU;DAT
data set-up time 100 - ns
t
HD;DAT
data hold time 0 - ns
t
SU;STO
set-up time for STOP
condition
0.6 - s
t
VD;DAT
data valid time 0 0.9 s
t
VD;ACK
data valid
acknowledge time
00.9s
t
SP
pulse width of spikes
that must be
suppressed by the
input filter
050ns
PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 35 of 52
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
Fig 25. I
2
C-bus timing diagram; rise and fall times refer to 30 % and 70 %
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PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 36 of 52
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
14. Application information
A 1 farad super capacitor combined with a low V
F
diode can be used as a standby or back-up
supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC
may operate for weeks.
Fig 26. Application diagram for PCF85063TP
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PCF85063TP/1Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Real Time Clock Low Power Real time clocks
Lifecycle:
New from this manufacturer.
Delivery:
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