PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 6 May 2015 25 of 52
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
9.5 I
2
C-bus protocol
9.5.1 Addressing
One I
2
C-bus slave address (1010001) is reserved for the PCF85063TP. The entire
I
2
C-bus slave address byte is shown in Table 29.
After a START condition, the I
2
C slave address has to be sent to the PCF85063TP device.
The R/W
bit defines the direction of the following single or multiple byte data transfer
(R/W
= 0 for writing, R/W = 1 for reading). For the format and the timing of the START
condition (S), the STOP condition (P) and the acknowledge bit (A) refer to the I
2
C-bus
characteristics (see Ref. 12 “
UM10204”). In the write mode, a data transfer is terminated
by sending either the STOP condition or the START condition of the next data transfer.
9.5.2 Clock and calendar READ or WRITE cycles
The I
2
C-bus configuration for the different PCF85063TP READ and WRITE cycles is
shown in Figure 17
and Figure 18. The register address is a 4-bit value that defines which
register will be accessed next. The upper 4 bits of the register address are not used.
Table 29. I
2
C slave address byte
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
1010001R/W
Fig 17. Master transmits to slave receiver (WRITE mode)
DFNQRZOHGJH
IURP3&)73
VODYHDGGUHVV ZULWHELW UHJLVWHUDGGUHVV
KWR$K
WRQ
GDWDE\WHV
