DSPIC30F1010T-30I/MM Datasheet DSPIC30F1010T-30I/MM, DSPIC30F1010T-30I/SO, DM300023 | P1-P3

 2008-2013 Microchip Technology Inc. DS80000391B-page 1

dsPIC30F1010/202X

The dsPIC30F1010/202X family devices that you have

received conform functionally to the current Device

Data Sheet (DS70178C), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the dsPIC30F1010/202X silicon.

Data Sheet clarifications and corrections start on

Page 17, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s pro-

grammers, debuggers, and emulation tools, which are

available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level

using MPLAB IDE in conjunction with a hardware

debugger:

1. Using the appropriate interface, connect the

device to the hardware debugger.

2. Open an MPLAB IDE project.

3. Configure the MPLAB IDE project for the

appropriate device and hardware debugger.

4. Based on the version of MPLAB IDE you are

using, do one of the following:

a) For MPLAB IDE 8, select Programmer >

Reconnect.

b) For MPLAB X IDE, select Window >

Dashboard and click the Refresh Debug

Tool Status icon ( ).

5. Depending on the development tool used, the

part number and Device Revision ID value

appear in the Output window.

The DEVREV values for the various

dsPIC30F1010/202X silicon revisions are shown in

Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A3).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

Revision ID for Silicon Revision

(1)

A0 A1 A2 A3

dsPIC30F1010 0x4040

0x1000 0x1001 0x1002 0x1003dsPIC30F2020 0x4000

dsPIC30F2023 0x4030

Note 1: Refer to the “dsPIC30F Family Reference Manual, Section 4. Program Memory” (DS70051) for detailed

information on Device and Revision IDs for your specific device.

dsPIC30F1010/202X Family Silicon Errata and

Data Sheet Clarification

dsPIC30F1010/202X

DS80000391B-page 2  2008-2013 Microchip Technology Inc.

TABLE 2: SILICON ISSUE SUMMARY

Module Feature

Item

Number

Issue Summary

Affected Revisions

(1)

A0 A1 A2 A3

PWM PWM Dead Time 1. If a value less than 0x0010 is written to

the DTRx and ALTDTRx registers, either

or both of the PWMxH and PWMxL

outputs will not function.

XXXX

PWM PWM Duty Cycle 2. Duty cycle resolution is not 1.1 ns over the

entire duty cycle range.

XXXX

PWM PWM Trigger 3. The PWM Special Event Trigger and

PWM Individual Trigger do not function

near the beginning of the PWM period.

XXXX

PWM PWM Override

Enable

4. The PWM override feature does not work

correctly.

XXXX

PWM PWM Duty Cycle 5. When the PWM module is operated with

immediate duty cycle updates enabled,

any duty cycle value less than or equal to

0x0010 causes the PWM outputs to flip to

the inverted state.

XXXX

PWM PWM Override

Priority

6. The PWM Fault, current-limit and output

override priorities do not work correctly.

XXXX

PWM PWM Jitter 7. The PWM output may exhibit an occa-

sional jitter proportional to the operating

speed of the dsPIC30F1010/202X devices.

XXXX

ADC ADC Global

Software Trigger

8. The Global Software Trigger bit

(GSWTRG in the ADCON register) is not

reset unless the PxRDY bits in the

ADSTAT register are reset.

XXXX

ADC ADC

Sample-and-Hold

Timing

9. The resolution of the PWM to ADC

Sample-and-Hold Trigger timing is 41.6 ns

instead of the 8 ns specified in the device

data sheet.

XXXX

ADC ADC Interrupts 10. Individual ADC interrupts for the ADC pin

pairs do not work.

XXXX

ADC ADC

Conversion Rate

11. The maximum conversion rate for the

ADC module is 1.5 Msps.

XXXX

PWM Current Reset

Mode

12. Setting the XPRES bit in the PWMCONx

source to reset the PWM period when the

PWM generated is configured in Indepen-

dent Time Base mode. This

functionality is not working correctly.

XXXX

Output

Compare

Output

Compare

Module

13. The output compare module will produce

a glitch on the output when an I/O pin is

initially set high and the module is config-

ured to drive the pin low at a specified

time.

XXXX

PWM Output

Compare

14. The output compare module will miss one

compare event when the Duty Cycle

0x0001.

XXXX

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

 2008-2013 Microchip Technology Inc. DS80000391B-page 3

dsPIC30F1010/202X

Output

Compare

Output Compare

Module

15. In Dual Compare Match mode, the OCx

output is not reset when the OCxR and

OCxRS registers are loaded with values

having a difference of 1.

XXXX

SPI SPI Module in

Slave Select Mode

16. The SPI module slave select functionality

will not work correctly.

XXXX

SPI SPI Module in

Frame Master

Mode

17. The SPI module will fail to generate frame

synchronization pulses in Frame Master

mode if FRMDLY = 1.

XXXX

SPI SPI Module 18. The SMP bit does not have any effect

when the SPI module is configured for a

1:1 prescale factor in Master mode.

XXXX

UART UART Module 19. If the Baud Rate Generator (BRG) register

contains an odd value and the parity

option is enabled, the module may falsely

indicate parity errors.

XXXX

UART UART Module 20. The Receive Buffer Overrun Error Status

bit (OERR) may be set prematurely.

XXXX

UART UART Module 21. UART receptions may be corrupted in

High Baud Rate mode (BRGH = 1).

XXXX

UART UART Module 22. The UTXISEL0 bit in the U1STA register

is always read as zero regardless of the

value written to it.

XXXX

UART UART Module 23. The auto-baud feature does not work

properly in High Baud Rate mode

(BRGH = 1).

XXXX

UART UART Module 24. When the auto-baud feature is enabled,

the Sync Break character (0x55) may be

loaded into the FIFO as data.

XXXX

UART UART Module

(IrDA

Reception)

25. The operation of the RXINV bit in the

U1MODE register is inverted.

XXXX

UART UART Module 26. The auto-baud feature measures baud

rate inaccurately for certain baud rate and

clock speed combinations.

XXXX

C™ Bus Collision 27. The Bus Collision Status bit (BCL) does

not get set when a bus collision occurs

during a Restart or Stop event.

XXXX

C 10-Bit Addressing

Mode

28. The I2CTRN register can be written to

even if a write collision is detected.

XXXX

C 10-Bit

Addressing Mode

29. The ACKSTAT bit does not reflect the

status of a transmission received from an

C™ slave device.

XXXX

C 10-Bit

Addressing Mode

30. The D_A status bit in the I2CSTAT register

does not get set on a write to the I2CTRN

C slave device.

XXXX

TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)

Module Feature

Item

Number

Issue Summary

Affected Revisions

(1)

A0 A1 A2 A3

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

DSPIC30F1010T-30I/MM

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