dsPIC30F1010/202X
DS80000391B-page 12 2008-2013 Microchip Technology Inc.
27. Module: I
2
C™
The Bus Collision Status bit (BCL) does not get set
when a bus collision occurs during a Restart or
Stop event. However, the BCL bit gets set when a
bus collision occurs during a Start event.
Work around
None.
Affected Silicon Revisions
28. Module: I
2
C
Writing to I2CTRN during a Start bit transmission
generates a write collision, indicated by the IWCOL
(I2CSTAT<7>) bit being set. In this state, additional
writes to the I2CTRN register should be blocked.
However, in this condition, the I2CTRN register can
be written, although transmissions will not occur
until the IWCOL bit is cleared in software.
Work around
After each write to the I2CTRN register, read the
IWCOL bit to ensure a collision has not occurred.
If the IWCOL bit is set, it must be cleared in
software and I2CTRN must be rewritten.
Affected Silicon Revisions
29. Module: I
2
C
The ACKSTAT bit (I2CSTAT<15>) only reflects
the received ACK/NACK status for master
transmissions, but not for slave transmissions. As
a result, a slave cannot use this bit to determine if
it received an ACK or a NACK from a master. In
future silicon revisions, the ACKSTAT bit will
reflect received ACK/NACK status for both master
and slave transmissions.
Work around
After transmitting a byte, the slave should poll the
SDA line (subject to a time-out period dependent
on the application) to determine if an ACK (0) or a
NACK (1) was received.
Affected Silicon Revisions
30. Module: I
2
C
The D_A Status bit (I2CSTAT<5>) gets set on a
slave data reception in the I2CRCV register, but
does not get set on a slave write to the I2CTRN
register. In future silicon revisions, the D_A bit will
get set on a slave write to I2CTRN.
Work around
Use the D_A status bit only for determining slave
reception status and not slave transmission status.
Affected Silicon Revisions
31. Module: MCLR
A brown-out event occurs when VDD drops below
the minimum operating voltage for the device, but
not all the way down to V
SS. When the dsPIC DSC
SMPS device is running with the PLL enabled, and
a brown-out event occurs, the device may stop
running and the MCLR
pin will not reset the device.
If this occurs, the device can only be reset by
cycling power to the VDD pins.
It is recommended that an external Brown-out
Reset (BOR) circuit be used to hold the device in
Reset, during a brown-out event, to overcome this
problem. The external BOR circuit will use the
MCLR
pin to hold the device in Reset. The
following work around, in combination with the
external BOR circuit, will ensure that the device is
cleanly reset after a brown-out event occurs.
Work around
The dsPIC DSC SMPS device must be powered
up with the PLL disabled, the Fail-Safe Clock
Monitor (FSCM) enabled and clock switching
enabled. The PLL should be enabled in software
via a clock switch after the device is reset (refer to
Section 29. “Oscillator” (DS70268) in the
“dsPIC30F Family Reference Manual” for details
on clock switching). This ensures that the MCLR
pin is functional and that the device can be reset
by an external BOR circuit (see Figure 1).
A0 A1 A2
A3
XXX
X
A0 A1 A2
A3
XXX
X
A0 A1 A2
A3
XXX
X
A0 A1 A2 A3
XXX
X
