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DSPIC30F1010T-30I/MM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
2008-2013 Microchip Technology Inc. DS80000391B-page 13
dsPIC30F1010/202X
FIGURE 1:
Use one of the following methods to achieve the
work around.
Method 1: Insert the code, shown in Example 1, at
the start of the program.
Method 2: Call the code, shown in Example 1, in
the beginning of code execution by including the
ClockSwitch.s file in the project and adding the
following code:
• For assembly programming, add the following
instruction at the beginning of the program:
.global __reset
…
…
__reset:
rcall ClockSwitch
…
…
• For C programming, add the following
instruction at the beginning of the program:
int main(void)
{
ClockSwitch;
…
…
}
EXAMPLE 1: CLOCK SWITCHING EXAMPLE
Affected Silicon Revisions
VSS
MCLR
+5V
+5V
R*
U2*
*Any commercially available BOR circuit can be used in this
configuration. Refer to the BOR circuit manufacturer’s data
sheet for exact circuit configuration.
dsPIC30F1010/202X
U1
External
BOR
Circuit
; This function performs a clock-switch from FRC to FRC+PLL. All other oscillator
; settings remain unchanged.
; Filename: ClockSwitch.s
_ClockSwitch:
mov #OSCCON+1,w4 ; Get address of high OSCCON byte
mov #0x0078, w0 ; 1st password for high byte access to OSCCON
mov #0x009A, w1 ; 2nd password for low byte access to OSCCON
mov #0x0001, w2 ; NOSC value for FRC+PLL
mov.b w0, [w4] ; Write 1st password
mov.b w1, [w4] ; Write 2nd password
mov.b w2, [w4] ; Write NOSC value
mov #OSCCON,w4 ; Get address of low OSCCON byte
mov #0x0046, w0 ; 1st password for high byte access to OSCCON
mov #0x0057, w1 ; 2nd password for low byte access to OSCCON
mov #0x0001, w2 ; Set OSWEN bit
mov.b w0, [w4] ; Write 1st password
mov.b w1, [w4] ; Write 2nd password
mov.b w2, [w4] ; Write OSWEN bit
return
A0 A1 A2 A3
XXX
X
dsPIC30F1010/202X
DS80000391B-page 14 2008-2013 Microchip Technology Inc.
32. Module: CPU
The Decimal Adjust instruction, DAW.b, may
improperly clear the Carry bit, C (SR<0>), when
executed.
Work around
Check the state of the Carry bit prior to executing
the DAW.b instruction. If the Carry bit is set, set the
Carry bit again after executing the DAW.b
instruction. Example 2 shows how the application
should process the Carry bit during a BCD addition
operation.
Affected Silicon Revisions
EXAMPLE 2: CHECK CARRY BIT BEFORE
DAW.b
33. Module: PWM
In Push-Pull mode, with immediate updates
enabled, the PWM pins may become swapped.
Work around
If using the PWM module in Push-Pull mode,
immediate updates must be disabled.
Affected Silicon Revisions
34. Module: PWM
The Dead-Time registers (DTRx/ALTDTRx) must
be modified only when the PWM is not running.
Adjusting the dead time “on-the-fly” can result in
an unpredictable glitch on the PWM output, which
may cause shoot-through.
Work around
None.
Affected Silicon Revisions
35. Module: UART
When the UART is configured for IR interface
operations (U1MODE<9:8> = 11), the 16x baud
rate clock signal on the BCLK pin is present only
when the module is transmitting. The pin is Idle at
all other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or is in an Idle state.
Affected Silicon Revisions
36. Module: UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
A0 A1 A2 A3
XXX
X
A0 A1 A2
A3
XXX
X
.include “p30fxxxx.inc”
.......
mov.b #0x80, w0 ;First BCD number
mov.b #0x80, w1 ;Second BCD number
add.b w0, w1, w2 ;Perform addition
bra NC, L0 ;If C set go to L0
daw.b w2 ;If not, do DAW and
bset.b SR, #C ;set the carry bit
bra L1 ;and exit
L0:daw.b w2
L1: ....
A0 A1 A2 A3
XXX
X
A0 A1 A2
A3
XXX
X
A0 A1 A2 A3
XXX
X
2008-2013 Microchip Technology Inc. DS80000391B-page 15
dsPIC30F1010/202X
37. Module: SPI
Setting the DISSCK bit in the SPIxCON1 register
does not allow the user application to use the SCK
pin as a general purpose I/O pin.
Work around
None.
Affected Silicon Revisions
38. Module: I
2
C
The BCL bit in I2CSTAT can only be cleared with a
16-bit operation and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
Work around
Use 16-bit operations to clear BCL.
Affected Silicon Revisions
39. Module: I
2
C
If there are two I
2
C devices on the bus, one of
them is acting as the master receiver and the other
as the slave transmitter. If both devices are config-
ured for 10-Bit Addressing mode, and have the
same value in the A10 and A9 bits of their
addresses, then when the slave select address is
sent from the master, both the master and slave
Acknowledge it. When the master sends out the
read operation, both the master and the slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
2
C devices, the addresses, as well as bits
A10 and A9, should be different.
Affected Silicon Revisions
40. Module: I
2
C
In 10-Bit Addressing mode, some address
matches do not set the RBF flag or load the I
2
C
Receive register, I2CRCV, if the lower address
byte matches the reserved addresses. In
particular, these include all addresses with the
form ‘xx0000xxxx’ and ‘xx1111xxxx’, with the
following exceptions:
• 001111000x
• 011111001x
• 101111010x
• 111111011x
Work around
The lower address byte in 10-Bit Addressing mode
shall not be a reserved address.
Affected Silicon Revisions
41. Module: I
2
C
If the I
2
C module is configured for a 10-bit slave with
an address of 0x102, the I2CRCV register content
for the lower address byte is 0x01, rather than 0x02.
However, the I
2
C module Acknowledges for both
address bytes.
Work around
None.
Affected Silicon Revisions
A0 A1 A2 A3
XXX
X
A0 A1 A2
A3
XXX
X
A0 A1 A2
A3
XXX
X
A0 A1 A2 A3
XXX
X
A0 A1 A2
A3
XXX
X
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

DSPIC30F1010T-30I/MM

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Buy DSPIC30F1010T-30I/MM
Manufacturer:
Microchip Technology
Description:
Digital Signal Processors & Controllers - DSP, DSC 6KB 256bytes-RAM 30MIPS 21I/O
Lifecycle:
New from this manufacturer.
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