2008-2013 Microchip Technology Inc. DS80000391B-page 5
dsPIC30F1010/202X
Silicon Errata Issues
1. Module: PWM
If dead-time functionality is enabled
(DTC<1:0> = 00 or 11 in the PWMCONx register),
the minimum usable value that can be written to the
Dead-Time registers, DTRx and ALTDTRx, is
0x0010. Writing a value less than 0x0010 will cause
either or both the PWMxH and PWMxL outputs not
to function. As a result of this erratum, the minimum
usable dead time is 16 ns. Dead-time resolution is
4 ns for dead times greater than 16 ns.
Work around
The dead time must either be disabled
(DTC<1:0> = 2) or DTRx and ALTDRx must have
a value of 0x0010 or greater. If zero dead time is
required, configure the DTC<1:0> bits in the
PWMCONx register to specify no dead time.
Affected Silicon Revisions
2. Module: PWM
The data sheet indicates that the power supply
PWM module has a 1.1 ns duty cycle resolution.
This is true for all values of PDCx except the
following:
1. 0x0010 < PDCx < 0x0040
2. (Period – 0x0040) < PDCx < (Period – 0x0010)
In these ranges, duty cycle resolution is 16 ns. The
PWM period is either the master period, PTPER,
or the individual PWM generator period, PHASEx.
Work around
If possible, the system should be designed so that
the PWM generator will operate in the duty cycle
range where the 1.1 ns resolution is possible. For
operation outside this range, the design must take
into account the reduced resolution.
Affected Silicon Revisions
3. Module: PWM
Each PWM generator can be configured to
generate a trigger for the ADC module or a trigger
interrupt at any point during the PWM period. The
point in time during the PWM period that the trigger
is set is specified in the TRIGx register for the
PWM Individual Trigger or in the SEVTCMP
register for the Special Event Trigger. The
minimum trigger value in TRIGx or SEVTCMP is
0x0008. Values below 0x0008 result in a PWM
Trigger not being initiated at all. As a result, no
ADC sampling or trigger interrupt will occur.
Work around
If the Special Event Trigger or the Individual
Trigger is implemented, the user should perform a
check in firmware to make sure that TRIGx and/or
SEVTCMP is always greater than 0x0008 and less
than the PWM period.
Affected Silicon Revisions
4. Module: PWM
The OVRDAT<1:0> bits in the IOCONx register
should determine the state of the PWMx output
pins when the OVRENH and OVRENL bits
(IOCONx<9:8>) are set. However, the PWM
override feature does not work correctly. The
PWMxH and PWMxL pins do not exhibit the state
specified by the OVRDAT<1:0> bits when only one
of the override bits (OVRENH or OVRENL) is set.
If both bits are set, the override state is exhibited
correctly on the PWMxL and PWMxH pins.
Work around
If override capability is desired on only one of the
PWM pin pairs, use the GPIO module to override
the PWM outputs. This can be done using the
PENH and PENL bits in the IOCONx register.
When the PENH/PENL bits in the IOCONx register
are cleared, the GPIO module assumes control of
the PWMxH/L output pin. The GPIO module must
be setup in advance for the desired override output
states and the pins must be configured as digital
outputs. This includes setting the PORTx and
TRISx registers correctly, which correspond to the
PWMxH and PWMxL pins.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (Rev. A3).
A0 A1 A2 A3
XXX
X
A0 A1 A2 A3
XXX
X
A0 A1 A2 A3
XXX
X
A0 A1 A2
A3
XXX
X
