dsPIC30F1010/202X
DS80000391B-page 16 2008-2013 Microchip Technology Inc.
42. Module: UART
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
• The UART receive interrupt is set to occur
when the FIFO is full or three-quarters full
(U1STA<7:6> = 1x), and
• More than two bytes with an error are received
In these two circumstances, only the first two bytes
with a parity or framing error will have the
corresponding bits indicate correctly. The error bits
will not be set after this.
Work around
None.
Affected Silicon Revisions
43. Module: PSV
An address error trap occurs in certain addressing
modes when accessing the first four bytes of a
Program Space Visibility (PSV) page. This only
occurs when using the following addressing
modes:
• MOV.D
• Register Indirect Addressing (Word or Byte
mode) with pre/post-decrement
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB
®
C30,
Version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum:
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 toolsuite for further details.
Affected Silicon Revisions
44. Module: FRC
The Oscillator Tuning Register (OSCTUN) has
four bits, TUN<3:0>, that allow the user to vary the
internal Fast RC (FRC) oscillator frequency. When
the OSCTUN register is set equal to ‘0b1111’ or
‘0b1110’, the FRC frequency does not match the
expected frequency. The user should avoid using
these two set values of the OSCTUN register.
Work around
Use any of the other permissible values for
OSCTUN to set the FRC frequency.
Affected Silicon Revisions
A0 A1 A2 A3
XXX
X
A0 A1 A2
A3
XXX
X
A0 A1 A2 A3
XXX
X
