2008-2013 Microchip Technology Inc. DS80000391B-page 7
dsPIC30F1010/202X
7. Module: PWM
The outputs of the PWM module may exhibit a
jitter proportional to the speed of operation of the
device. The jitter may be observed as a deviation
in the PWM period, duty cycle or phase, and may
be affected independent of each other. As a result,
the maximum deviation exhibited on the PWM
output pin at 30 MIPS is 8.4 nsec.
The jitter is caused by silicon process variations,
noise on the V
DD rail and the operating temperature
of the dsPIC DSC. However, for a given set of
operating conditions, the maximum jitter will be the
same for all three parameters and independent of
each other. Table 1 shows the maximum jitter that
may be exhibited at various operating speeds.
TABLE 1:
The maximum jitter at any operating speed can be
determined using Equation 2.
EQUATION 2:
Where:
• S is the speed of operation in MIPS.
The maximum percentage error observed on the
PWM output can be calculated using Equation 3.
EQUATION 3:
Where:
• x
observed
is the observed value of parameter of
interest (PWM period, duty cycle or phase).
• x
programmed
is the programmed value of
parameter of interest (PWM period, duty cycle
or phase).
Work around
Operate the power supply PWM module so that
the percentage error in the parameter of interest
(from Equation 3) is within permissible limits of the
application.
Affected Silicon Revisions
8. Module: ADC
In order to perform multiple Analog-to-Digital
conversions using the Global Software Trigger, the
PxRDY bits in the ADSTAT register must be
cleared. The data sheet indicates that the user can
configure the ADC pin pairs to perform a
conversion when the GSWTRG bit in the ADCON
register is set. When the conversion is available,
the user must then clear the GSWTRG bit and set
it again to perform another conversion. Contrary to
what the data sheet indicates, this will not initiate
another conversion unless the PxRDY bits are
cleared. Clearing the PxRDY bits automatically
clears the GSWTRG bit.
This only applies to a polling-based approach. If an
interrupt-based approach is used, the user is
required to clear the PxRDY bits in the ADC
Interrupt Service Routine (ISR).
Work around
The following sequence should be followed to
manually trigger ADC conversions using the
Global Software Trigger (polling based only.)
1. Set the GSWTRG bit in ADCON to initiate a
conversion on channels which have the trigger
source as the Global Software Trigger (via the
TRGSRCx<4:0> bits in the ADCPCx
registers).
2. Check the PxRDY bits to determine when the
conversion(s) is completed.
3. Clear the PxRDY bits. The GSWTRG bit will be
cleared as a result of this operation.
4. Repeat Steps 1 to 3 to perform additional
conversions.
Alternatively, the Individual Software Trigger can
be selected by setting the TRGSRCx<5:0> bits in
the ADCPCx register equal to 0x01. Instead of
using the Global Software Trigger, the Individual
Software Trigger (ADCPCx<SWTRGx>) bits can
be used to trigger a conversion on a given analog
pin pair. In a bit polling approach, the PENDx in the
ADCPCx register should be used to determine
when a conversion is completed. In an interrupt
based approach, the PxRDY bits get set when the
conversion is complete. This bit must be cleared in
the ADC Interrupt Service Routine in order to
enable future interrupts.
Affected Silicon Revisions
Speed of Operation
Maximum Jitter on
PWM Output
30 MIPS 8.4 nsec
20 MIPS 12.6 nsec
15 MIPS 16.8 nsec
A0 A1 A2 A3
XXX
X
Maximum Jitter Observed (nsec) =
252
(S)
x
programmed
x
observed
–
x
programmed
---------------------------------------------------------------
100=
Error (%)
A0 A1 A2 A3
XXX
X
