Document Number: 001-63745 Rev. *D Page 3 of 37
PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional microcontroller unit (MCU)-based system
components with one, low-cost single-chip programmable
component. A PSoC device includes configurable blocks of
analog and digital logic, and programmable interconnect. This
architecture makes it possible for you to create customized
peripheral configurations, to match the requirements of each
individual application. Additionally, a fast CPU, flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts.
The PSoC architecture, as illustrated in the “Logic Block
Diagram” on page 1, comprises of four main areas: the core, the
system resources, the digital system, and the analog system.
Configurable global bus resources allow all the device resources
to be combined into a complete custom system. Each
CY8C21x12 device includes one limited digital block and one
CapSense block. Depending on the PSoC package, up to 24
GPIOs are also included. The GPIOs provide access to the
global digital and analog interconnects.
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep, and watchdog timers, and an internal
main oscillator (IMO) and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System Resources provide additional capability, such as digital
clocks for increased flexibility, I
2
C functionality for implementing
an I
2
C master, slave, or multi-master, an internal voltage
reference that provides an absolute value of 1.3 V to a number
of PSoC subsystems, and various system resets supported by
the M8C.
The Digital System is composed of a programmable limited
digital block and fixed-function digital resources inside the
CapSense block. The limited digital block can be configured into
a number of digital peripherals. The fixed-function digital
resources in the CapSense block provide external modulation
signals, measurement timing, and measurement conversion.
The digital resources can be connected to the GPIO through a
series of global buses that provide very flexible routing options.
The Analog System is composed of a comparator and a filter that
are used in the CapSense block to implement capacitive sensing
measurement.
The Digital System
The Digital System is composed of one digital block. This block
is an 8-bit resource that can implement various 8-bit digital
peripherals. Digital peripheral configurations include those listed.
■ PWM (8-bit)
■ Counter (8-bit)
■ Timer (8-bit)
■ Half-duplex 8-bit UART with selectable parity
■ SPI slave
■ I
2
C master, slave, or multi-master (implemented in a dedicated
I
2
C block)
The digital block can be connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic opera-
tions. This configurability frees your designs from the constraints
of a fixed peripheral controller.
Figure 1. Digital System Block Diagram
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digital Array
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
LDB0
4
3
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 2
CapSense0
Analog Digital
Port 3 Port 1
Port 0
