Document Number: 001-63745 Rev. *D Page 15 of 37
DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Table 6. DC Chip Level Specifications
Symbol Description Min Typ Max Units Notes
V
DD
Supply voltage 3.0 – 5.25 V See table titled DC POR and LVD Specifi-
cations on page 16
I
DD
Supply current, IMO = 24 MHz – 4 6 mA Conditions are V
DD
= 5.25 V, CPU =
3 MHz, 48 MHz disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz
I
DD3
Supply current, IMO = 6 MHz using
SLIMO mode
– 2 4 mA Conditions are V
DD
= 3.3 V, CPU =
3 MHz, 48 MHz disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz
I
SB1
Sleep (mode) current with POR, LVD,
sleep timer, WDT, and ILO active
– 2.8 7 A V
DD
= 3.3 V, –40 C T
A
85 C
I
SB2
Sleep (mode) current with POR, LVD,
sleep timer, WDT, and ILO active
– 5 15 A V
DD
= 5.25 V, –40 C T
A
85 C
V
REF
Reference voltage (Bandgap) 1.28 1.30 1.32 V Trimmed for appropriate V
DD
range
Table 7. DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
R
PU
Pull-up resistor 4 5.6 8 k
R
PD
Pull-down resistor 4 5.6 8 k Also applies to the internal pull-down
resistor on the XRES pin
V
OH
High output level V
DD
– 1.0 – – V I
OH
= 10 mA, V
DD
= 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5]))
V
OL
Low output level – – 0.75 V I
OL
= 25 mA, V
DD
= 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5]))
I
OH
High level source current 10 – – mA V
OH
V
DD
– 1.0 V, see the limitations of
the total current in the note for V
OH
I
OL
Low level sink current 25 – – mA V
OL
0.75 V, see the limitations of the
total current in the note for V
OL
V
IL
Input low level – – 0.8 V
V
IH
Input high level 2.1 – V
V
H
Input hysteresis – 60 – mV
I
IL
Input leakage (absolute value) – 1 – nA Gross tested to 1 A.
C
IN
Capacitive load on pins as input – 3.5 10 pF Package and pin dependent
Temp = 25 C
C
OUT
Capacitive load on pins as output – 3.5 10 pF Package and pin dependent
Temp = 25 C
