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CY8C21512-24PVXAT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 10 of 37
Registers
Register Conventions
This section lists the registers of the CY8C21x12 PSoC device.
For detailed register information, refer to the PSoC Technical
Reference Manual.
The register conventions specific to this section are listed in the
following table.
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks, bank 0 and bank 1. The XIO bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XIO bit is set to ‘1’, the user is in bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 11 of 37
Table 4. Register Map 0 Table: User Space
Name
Addr
(0,Hex)
Access Name
Addr
(0,Hex)
Access Name
Addr
(0,Hex)
Access Name
Addr
(0,Hex)
Access
PRT0DR 00 RW 40 80 C0
PRT0IE 01 RW 41 81 C1
PRT0GS 02 RW 42 82 C2
PRT0DM2 03 RW 43 83 C3
PRT1DR 04 RW 44 CSREF_CR1 84 RW C4
PRT1IE 05 RW 45 85 C5
PRT1GS 06 RW 46 86 C6
PRT1DM2 07 RW 47 87 C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 90 CUR_PP D0 RW
11 51 91 STK_PP D1 RW
12 52 92 D2
13 53 93 IDX_PP D3 RW
14 54 94 MVR_PP D4 RW
15 55 95 MVW_PP D5 RW
16 56 96 I2C_CFG D6 RW
17 57 97 I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
CSCNT_DR0 20 # 60 A0 INT_MSK0 E0 RW
CSCNT_DR1 21 W AMUX_CFG 61 RW A1 INT_MSK1 E1 RW
CSCNT_DR2 22 RW CSCMP_CR0 62 RW A2 INT_VC E2 RC
CSCNT_CR0 23 # 63 A3 RES_WDT E3 W
CSMOD0_DR0 24 # CSCMP_CR1 64 # A4 E4
CSMOD0_DR1 25 W 65 A5 E5
CSMOD0_DR2 26 RW CSCMP_CR2 66 RW A6 CSCMP_CR5 E6 RW
CSMOD0_CR0 27 # 67 A7 CSCMP_CR6 E7 RW
CSMOD1_DR0 28 # 68 A8 E8
CSMOD1_DR1 29 W CSREF_CR0 69 # A9 E9
CSMOD1_DR2 2A RW 6A AA EA
CSMOD1_CR0 2B # 6B AB EB
LDB0_DR0 2C # TMP_DR0 6C RW AC EC
LDB0_DR1 2D W TMP_DR1 6D RW AD ED
LDB0_DR2 2E RW TMP_DR2 6E RW AE EE
LDB0_CR0 2F # TMP_DR3 6F RW AF EF
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 72 RDI0IS B2 RW F2
33 73 RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 CSCMP_CR3 76 RW RDI0RO1 B6 RW F6
37 CSCMP_CR4 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and must not be accessed. # Access is bit specific.
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 12 of 37
Table 5. Register Map 1 Table: Configuration Space
Name
Addr
(1,Hex)
Access Name
Addr
(1,Hex)
Access Name
Addr
(1,Hex)
Access Name
Addr
(1,Hex)
Access
PRT0DM0 00 RW 40 80 C0
PRT0DM1 01 RW 41 81 C1
PRT0IC0 02 RW 42 82 C2
PRT0IC1 03 RW 43 83 C3
PRT1DM0 04 RW 44 84 C4
PRT1DM1 05 RW 45 85 C5
PRT1IC0 06 RW 46 86 C6
PRT1IC1 07 RW 47 87 C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
0C 4C 8C CC
0D 4D 8D CD
0E 4E 8E CE
0F 4F 8F CF
10 50 90 GDI_O_IN D0 RW
11 51 91 GDI_E_IN D1 RW
12 52 92 GDI_O_OU D2 RW
13 53 93 GDI_E_OU D3 RW
14 54 94 D4
15 55 95 D5
16 56 96 D6
17 57 97 D7
18 58 98 MUX_CR0 D8 RW
19 59 99 MUX_CR1 D9 RW
1A 5A 9A MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C DC
1D 5D 9D DD
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
CSCNT_CR1 20 RW CSCLK_CR0 60 RW A0 OSC_CR0 E0 RW
CSCNT_CR2 21 RW CSCLK_CR1 61 RW A1 OSC_CR1 E1 RW
CSCNT_CR3 22 RW 62 A2 OSC_CR2 E2 RW
23 CSREF_CR2 63 RW A3 VLT_CR E3 RW
CSMOD0_CR1 24 RW CSCMP_CR7 64 RW A4 VLT_CMP E4 R
CSMOD0_CR2 25 RW 65 A5 E5
CSMOD0_CR3 26 RW CSREF_CR3 66 RW A6 CSREF_CR4 E6 RW
27 CSCMP_CR8 67 RW A7 E7
CSMOD1_CR1 28 RW 68 A8 IMO_TR E8 W
CSMOD1_CR2 29 RW 69 A9 ILO_TR E9 W
CSMOD1_CR3 2A RW 6A AA BDG_TR EA RW
2B CSCLK_CR2 6B RW AB ECO_TR EB W
LDB0_FN 2C RW TMP_DR0 6C RW AC EC
LDB0_IN 2D RW TMP_DR1 6D RW AD ED
LDB0_OU 2E RW TMP_DR2 6E RW AE EE
2F TMP_DR3 6F RW AF EF
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 72 RDI0IS B2 RW F2
33 73 RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 76 RDI0RO1 B6 RW F6
37 77 B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD FD
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are Reserved and must not be accessed. # Access is bit specific.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

CY8C21512-24PVXAT

Mfr. #:
Buy CY8C21512-24PVXAT
Manufacturer:
Cypress Semiconductor
Description:
8-bit Microcontrollers - MCU 24 I/O 8K FLASH 512 BYTES SRAM
Lifecycle:
New from this manufacturer.
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