Document Number: 001-63745 Rev. *D Page 21 of 37
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Table 16. 5-V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
F
OSCEXT
Frequency 0.093 – 24.6 MHz
– High period 20.6
– 5300 ns
– Low period 20.6 – –ns
– Power-up IMO to switch 150
– – s
Table 17. 3.3-V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
F
OSCEXT
Frequency with CPU clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz
at 3.3 V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
F
OSCEXT
Frequency with CPU clock divide by 2 or
greater
0.186 – 24.6 MHz If the frequency of the external clock
is greater than 12 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
– High period with CPU clock divide by 1 41.7
– 5300 ns
– Low period with CPU clock divide by 1 41.7 – –ns
– Power-up IMO to switch 150
– – s
Table 18. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
t
RSCLK
Rise time of SCLK 1 – 20 ns
t
FSCLK
Fall time of SCLK 1 – 20 ns
t
SSCLK
Data setup time to falling edge of SCLK 40 – – ns
t
HSCLK
Data hold time from falling edge of SCLK 40 – – ns
t
SCLK
Frequency of SCLK 0 – 8 MHz
t
ERASEB
Flash block erase time – 10 40
[16]
ms
t
WRITE
Flash block write time – 40 160
[16]
ms
t
DSCLK
Data out delay from falling edge of SCLK – 38 45 ns 3.6 V
DD
t
DSCLK3
Data out delay from falling edge of SCLK – 44 50 ns 3.0 V
DD
3.6
t
PRGH
Total flash block program time
(t
ERASEB
+ t
WRITE
), hot
– – 100
[16]
ms T
J
0 C
t
PRGC
Total flash block program time
(t
ERASEB
+ t
WRITE
), cold
– – 200
[16]
ms T
J
0 C
Note
16. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
