CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 7 of 37
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called "user modules." User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. For example,
a PWM User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the "Generate
Configuration Files" step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer's Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabil-
ities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 8 of 37
Pinouts
TheCY8C21x12 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, V
SS
, V
DD
, and XRES are not
capable of digital I/O.
20-Pin Part Pinout
Table 2. 20-Pin Part Pinout (shrink small-outline package (SSOP))
Pin
No.
Type
Name Description
Figure 3. CY8C21312 20-Pin PSoC Device
Digital Analog
1 I/O I, M P0[7] Analog column mux input
2 I/O I, M P0[5] Analog column mux input
3 I/O I, M P0[3] Analog column mux input, C
MOD
capacitor pin
4 I/O I, M P0[1] Analog column mux input, C
MOD
capacitor pin
5 Power
V
SS
Ground connection
6 I/O M P1[7] I
2
C serial clock (SCL)
7 I/O M P1[5] I
2
C serial data (SDA)
8 I/O M P1[3]
9 I/O M P1[1] I
2
C SCL, ISSP-SCLK
[4]
10 Power
V
SS
Ground connection
11 I/O M P1[0] I
2
C SDA, ISSP-SDATA
[4]
12 I/O M P1[2]
13 I/O M P1[4] Optional external clock input (EXTCLK)
14 I/O M P1[6]
15 Input XRES Active high external reset with internal
pull-down
16 I/O I, M P0[0] Analog column mux input
17 I/O I, M P0[2] Analog column mux input
18 I/O I, M P0[4] Analog column mux input
19 I/O I, M P0[6] Analog column mux input
20 Power
V
DD
Supply voltage
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
4. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 9 of 37
28-Pin Part Pinout
Note
5. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Table 3. 28-Pin Part Pinout (SSOP)
Pin
No.
Type
Name Description
Figure 4. CY8C21512 28-Pin PSoC Device
Digital Analog
1 I/O I, M P0[7] Analog column mux input
2 I/O I, M P0[5] Analog column mux input
3 I/O I, M P0[3] Analog column mux input, C
MOD
capacitor pin
4 I/O I, M P0[1] Analog column mux input, C
MOD
capacitor pin
5 I/O M P2[7]
6 I/O M P2[5]
7 I/O M P2[3]
8 I/O M P2[1]
9 Power
V
SS
Ground connection
10 I/O M P1[7] I
2
C SCL
11 I/O M P1[5] I
2
C SDA
12 I/O M P1[3]
13 I/O M P1[1] I
2
C SCL, ISSP-SCLK
[5]
14 Power
V
SS
Ground connection
15 I/O M P1[0] I
2
C SDA, ISSP-SDATA
[5]
16 I/O M P1[2]
17 I/O M P1[4] Optional EXTCLK
18 I/O M P1[6]
19 Input XRES Active high external reset with internal
pull-down
20 I/O M P2[0]
21 I/O M P2[2]
22 I/O M P2[4]
23 I/O M P2[6]
24 I/O I, M P0[0] Analog column mux input
25 I/O I, M P0[2] Analog column mux input
26 I/O I, M P0[4] Analog column mux input
27 I/O I, M P0[6] Analog column mux input
28 Power
V
DD
Supply voltage
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
SSOP
1
AI, M, P0[7]
AI, M, P0[5]
AI, M, P0[3]
AI, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
V
SS
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M, P1[1]
V
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], M, EXTCLK
P1[2], M
P1[0], M, I2C SDA

CY8C21512-24PVXAT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
8-bit Microcontrollers - MCU 24 I/O 8K FLASH 512 BYTES SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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