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CY8C21512-24PVXAT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 16 of 37
DC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
These comparator electrical specifications apply to the comparator in the CapSense block.
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Table 8. DC Comparator Specifications
Symbol Description Min Typ Max Units Notes
V
OSCMP
Input offset voltage (absolute value) – 2.5 15 mV
TCV
OSCMP
Average input offset voltage drift – 10 – V/C
I
EBCMP
[6]
Input leakage current (Port 0 analog pins) – 200 – pA Gross tested to 1 A
C
INCMP
Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent
Temp = 25 C
V
CMCMP
Common mode voltage range 0.0 – V
DD
– 1 V
G
OLCMP
Open loop gain – 80 – dB
I
SCMP
Supply current
3.0 V V
DD
3.6 V – 30 – A
4.75 V V
DD
5.25 V – 35 – A
Notes
6. Atypical behavior:
I
EBOA
of Port 0 Pin 0 is below 1 nA at 25 C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 pA.
7. Always greater than 50 mV above V
PPOR1
(PORLEV[1:0] = 01b) for falling supply.
Table 9. DC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
R
SW
Switch resistance to common analog bus – – 400
R
VDD
Resistance of initialization switch to V
DD
– – 800
Table 10. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
V
PPOR0
V
PPOR1
V
PPOR2
V
DD
value for precision POR (PPOR) trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
V
DD
must be greater than or
equal to 2.5 V during startup,
reset from the XRES pin, or reset
from watchdog.
V
LVD1
V
LVD2
V
LVD3
V
LVD4
V
LVD5
V
LVD6
V
LVD7
V
DD
value for LVD trip
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.99
[7]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 17 of 37
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Table 11. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
V
DDP
V
DD
for programming and erase 4.5 5 5.5 V This specification applies to
the functional requirements of
external programmer tools
V
DDLV
Low V
DD
for verify 3.0 3.1 3.2 V This specification applies to
the functional requirements of
external programmer tools
V
DDHV
High V
DD
for verify 5.1 5.2 5.3 V This specification applies to
the functional requirements of
external programmer tools
V
DDIWRITE
Supply voltage for flash write operation 3.0 – 5.25 V This specification applies to
this device when it is
executing internal flash writes
I
DDP
Supply current during programming or verify – 5 25 mA
V
ILP
Input low voltage during programming or verify – – 0.8 V
V
IHP
Input high voltage during programming or verify 2.2 – – V
I
ILP
Input current when applying V
ILP
to P1[0] or
P1[1] during programming or verify
– – 0.2 mA Driving internal pull-down
resistor
I
IHP
Input current when applying V
IHP
to P1[0] or
P1[1] during programming or verify
– – 1.5 mA Driving internal pull-down
resistor
V
OLV
Output low voltage during programming or
verify
– – 0.75 V
V
OHV
Output high voltage during programming or
verify
V
DD
– 1.0 – V
DD
V
Flash
ENPB
Flash endurance (per block)
[8, 9]
1,000 – – – Erase/write cycles per block
Flash
ENT
Flash endurance (total)
[9, 10]
128,000 – – – Erase/write cycles
Flash
DR
Flash data retention 15 – – Years
Notes
8. The erase/write cycle limit per block (Flash
ENPB
) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to
5.25 V.
9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
10. The maximum total number of allowed erase/write cycles is the minimum Flash
ENPB
value multiplied by the number of flash blocks in the device.
CY8C21312, CY8C21512
Document Number: 001-63745 Rev. *D Page 18 of 37
AC Electrical Characteristics
AC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C T
A
85 C or 3.0 V to 3.6 V and –40 C T
A
85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Table 12. AC Chip Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO24
IMO frequency for 24 MHz 22.8
[11]
24 25.2
[11]
MHz Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 6 on page 13.
SLIMO mode = 0.
F
IMO6
IMO frequency for 6 MHz 5.5
[11]
6 6.5
[11]
MHz Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 6 on page 13.
SLIMO mode = 1.
F
CPU1
CPU frequency (5 V V
DD
nominal) 0.089
[11]
24 25.2
[11]
MHz 24 MHz only for SLIMO mode = 0
F
CPU2
CPU frequency (3.3 V V
DD
nominal) 0.089
[11]
12 12.6
[11]
MHz
F
BLK5
Digital PSoC block frequency
0
(5 V V
DD
nominal)
0 48 50.4
[11,12]
MHz Refer to the AC Digital Block
Specifications below
F
BLK33.
Digital PSoC block frequency (3.3 V V
DD
nominal)
0 24 25.2
[11, 12]
MHz Refer to the AC Digital Block
Specifications below
F
32K1
ILO frequency 15 32 64 kHz This specification applies when
the ILO has been trimmed
F
32KU
ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C
processor starts to execute, the
ILO is not trimmed.
t
XRST
External reset pulse width 10 – – s
DC24M 24 MHz duty cycle 40 50 60 %
DC
ILO
ILO duty cycle 20 50 80 %
Step24M 24 MHz trim step size – 50 – kHz
Fout48M 48 MHz output frequency 45.6
[11]
48.0 50.4
[11]
MHz
F
MAX
Maximum frequency of signal on row
input or row output
– – 12.6 MHz
SR
POWERUP
Power supply slew rate – – 250 V/ms V
DD
slew rate during power-up
t
POWERUP
Time between end of POR state and
CPU code execution
– 16 100 ms Power-up from 0 V.
t
JIT_IMO
[13]
24 MHz IMO cycle-to-cycle jitter (RMS) – 200 700 ps
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
– 300 900
ps
N = 32
24 MHz IMO period jitter (RMS) – 100 400
ps
Notes
11. Accuracy derived from IMO with appropriate trim for V
DD
range.
12. See the individual user module datasheets for information on maximum frequencies for user modules.
13. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
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CY8C21512-24PVXAT

Mfr. #:
Buy CY8C21512-24PVXAT
Manufacturer:
Cypress Semiconductor
Description:
8-bit Microcontrollers - MCU 24 I/O 8K FLASH 512 BYTES SRAM
Lifecycle:
New from this manufacturer.
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