ADuCRF101 Data Sheet
SPI Timing
SPI timing is guaranteed by design and not production tested.
SPI Master Mode Timing
Table 5.
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width
1
(SPIDIV
2
+ 1) × t
UCLK
ns
t
SH
SCLK high pulse width
1
(SPIDIV
2
+ 1) × t
UCLK
ns
t
DAV
Data output valid after SCLK edge 0 32.0 ns
t
DOSU
Data output setup before SCLK edge
1
(SPIDIV
2
+ 1) × t
UCLK
ns
t
DSU
Data input setup time before SCLK edge 59.8 ns
t
DHD
Data input hold time after SCLK edge 16.0 ns
t
DF
Data output fall time 10.6 32.0 ns
t
DR
Data output rise time 10.6 32.0 ns
t
SR
SCLK rise time 10.6 32.0 ns
t
SF
SCLK fall time 10.6 32.0 ns
1
t
UCLK
= 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
2
For more information about SPIDIV, see the UG-231 User Guide.
SCLK
(POLARITY = 0)
CS
SCLK
(POLARITY = 1)
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
SH
t
SL
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
1/2 SCLK
CYCLE
3/4 SCLK
CYCLE
09464-012
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
CS
1 SCLK
CYCLE
3/4 SCLK
CYCLE
09464-013
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. A | Page 10 of 19
