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ADUCRF101BCPZ128R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
ADuCRF101 Data Sheet
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted
Table 7.
Parameter Rating
AVDD, IOVDD, VDDBAT1, and VDDBAT2 to GND −0.3 V to +3.96 V
Digital Input Voltage to GND −0.3 V to +3.96 V
Digital Output Voltage to GND −0.3 V to +3.96 V
VREF to GND −0.3 V to +3.96 V
Analog Inputs to GND −0.3 V to +2.1 V
ESD (Human Body Model) ±2.5 kV
Temperature
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 105°C
Peak Solder Reflow Temperature
Pb-Free Assemblies (30 sec) 260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Th
e exposed package paddle must be soldered to a metal pad
on the printed circuit board (PCB) and connected to ground.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 8. Thermal Resistance
Package Type θ
JA
Unit
64-Lead LFCSP_VQ 35 °C/W
ESD CAUTION
Rev. A | Page 12 of 19
.
Data Sheet ADuCRF101
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDDVCO
LVDD2
SWDIO
GND
IOVDD
SWCLK
VCOGUARD
VDDSYNTH
CWAKE
XOSC26P
XOSC26N
DGUARD
VDD_DIG1
P1.5/IRQ6/I2CSDA/PWM7
P1.4/IRQ5/I2CSCL/PWM6
P1.3/PWM5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P3.5
P3.4
P3.3/PWMTRIP
P3.2/PWMSYNC
ADCVREF
P4.7/PWM7
P4.6/PWM6
VDDBAT1
VDD_DIG2
LFXTAL1
LFXTAL2
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3
P4.2/PWM2
P4.1/PWM1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDRF1
RBIAS
VDDRF2
RFIO_1P
RFIO_1N
RFO2
VDDBAT2
AVDD
VREF
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
LVDD1
P4.0/PWM0
RESET
BM/P0.6/IRQ2/CS3/RTS/PWM0
P0.7/IRQ3/CS4/CTS
IOVDD
P0.0/MISO
P0.1/SCLK
P0.2/MOSI/PWM0
P2.4/IRQ8
P0.3/IRQ1/CS0/ADCCONVST/PWM1
P2.6
P0.4/CS1/ECLKOUT
P0.5/CS2/ECLKIN
P1.0/RXD/IRQ4/MOSI/PWM2
P1.1/POR/TXD/PWM3
P1.2/PWM4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADuCRF101
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PACKAGE PADDLE MUST BE SOLDERED TO A METAL PAD ON
THE PCB AND CONNECTED TO GROUND.
09464-010
Fi
gure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin
No. Mnemonic Description
1 VDDRF1
Voltage Regulator Output for RF Block. For regulator stability and noise rejection, place a
220 nF capacitor between this pin and ground.
2
RBIAS
External Bias Resistor. Use a 36 kΩ resistor with 2% tolerance.
3 VDDRF2
Voltage Regulator Output for RF Block. For regulator stability and noise rejection, place a
220 nF capacitor between this pin and ground.
4 RFIO_1P LNA Positive Input in Receive Mode; Differential PA Positive Output in Transmit Mode.
5 RFIO_1N LNA Negative Input in Receive Mode; Differential PA Negative Output in Transmit Mode.
6 RFO2 Single-Ended PA Output.
7 VDDBAT2 Battery Terminal
1
. Supply for the LDOs used in the RF section of the transceiver.
8 AVDD
Battery Terminal
1
. Supply for the analog circuits such as the ADC and ADC internal
reference, POR, PSM, and LDOs.
9 VREF Internal 1.25 V ADC Reference. Place a 0.47 µF capacitor between this pin and ground.
10 ADC0 ADC Input Channel 0. Input of DIFF0 pair in differential mode.
2
11
ADC1
ADC Input Channel 1. Input of DIFF0 pair in differential mode.
2
12 ADC2 ADC Input Channel 2. Input of DIFF1 pair in differential mode.
2
13 ADC3 ADC Input Channel 3. Input of DIFF1 pair in differential mode.
2
14 ADC4 ADC Input Channel 4. Input of DIFF2 pair in differential mode.
2
15 ADC5 ADC Input Channel 5. Input of DIFF2 pair in differential mode.
2
16 LVDD1
On-Chip LDO Decoupling Output. Connect a 0.47 µF capacitor to the 1.8 V output to
ensure that the core operating voltage is stable. For correct operation, connect a 1 µF
capacitor between this pin and LVDD2 (Pin 18).
Rev. A | Page 13 of 19
ADuCRF101 Data Sheet
Pin
No. Mnemonic Description
17 VDDVCO
Voltage Regulator Output for Voltage Controlled Oscillator (VCO). For regulator stability
and noise rejection, place a 220 nF capacitor between this pin and ground.
18 LVDD2
On-Chip LDO Decoupling Output. Connect a 0.47 µF capacitor to the 1.32 V output to
ensure that the core operating voltage is stable. For correct operation, connect a 1 µF
capacitor between this pin and LVDD1( Pin 16).
19 SWDIO Serial Wire Bidirectional Data.
20 GND Ground. Connect this pin to the exposed pad.
21 IOVDD General-Purpose I/O Supply
1
. Connect this pin to the battery terminal.
22
SWCLK
Serial Wire Debug Clock.
23 VCOGUARD Guard, Screen for VCO. Connect this pin to VDDVCO.
24 VDDSYNTH
Voltage Regulator Output for Synthesizer. For regulator stability and noise rejection,
place a 220 nF capacitor between this pin and ground.
25 CWAKE
External Capacitor for Wake-Up Control. Place a 150 nF capacitor between this pin and
ground.
26
XOSC26P
Connect the 26 MHz reference crystal between this pin and XOSC26N (HFXTAL).
3
27 XOSC26N Connect the 26 MHz reference crystal between this pin and XOSC26P (HFXTAL).
28 DGUARD Internal Guard, Screen for Digital Cells. Connect this pin to VDD_DIG1.
29 VDD_DIG1
Voltage Regulator Output for the Digital Section of the Transceiver. For regulator stability
and noise rejection, place a 220 nF capacitor between this pin and ground.
30
P1.5/IRQ6/I2CSDA/PWM7
General-Purpose Input and Output Port 1.5 (P1.5).
External Interrupt 6 (IRQ6).
I
2
C Serial Data (I2CSDA).
PWM Channel 7 (PWM7).
31 P1.4/IRQ5/I2CSCL/PWM6 General-Purpose Input and Output Port 1.4 (P1.4).
External Interrupt 5 (IRQ5).
I
2
C Serial Clock (I2CSCL).
PWM Channel 6 (PWM6).
32 P1.3/PWM5 General-Purpose Input and Output Port 1.3 (P1.3).
PWM Channel 5 (PWM5).
33 P1.2/PWM4 General-Purpose Input and Output Port 1.2 (P1.2).
PWM Channel 4 (PWM4).
34
P1.1/
POR/TXD/PWM3
General-Purpose Input and Output Port 1.1 (P1.1).
Power-On Reset Output (
POR).
UART TXD (TXD).
PWM Channel 3 (PWM3).
35 P1.0/RXD/IRQ4/MOSI/PWM2 General-Purpose Input and Output Port 1.0 (P1.0).
UART RXD (RXD).
External Interrupt 4 (IRQ4).
SPI1 Master Out, Slave In (MOSI).
PWM Channel 2 (PWM2).
36
P0.5/
CS2/ECLKIN
General-Purpose Input and Output Port 0.5 (P0.5).
SPI1 Chip Select 2 (
CS2).
External Clock Input (ECLKIN).
37
P0.4/
CS1/ECLKOUT
General-Purpose Input and Output Port 0.4 (P0.4).
SPI1 Chip Select 1 (
CS1).
External Clock Output (ECLKOUT).
38 P2.6
General-Purpose Input and Output Port 2.6. Do not connect this pin. This pin is
connected internally to the RF transceiver. It can be used for BER measurements.
39
P0.3/IRQ1/
CS0/ADCCONVST/PWM1
General-Purpose Input and Output Port 0.3 (P0.3).
External Interrupt 1 (IRQ1).
SPI1 Chip Select 0 (
CS0).
ADC Convert Start (ADCCONVST).
PWM Channel 1 (PWM1).
Rev. A | Page 14 of 19
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ADUCRF101BCPZ128R7

Mfr. #:
Buy ADUCRF101BCPZ128R7
Manufacturer:
Analog Devices Inc.
Description:
RF Microcontrollers - MCU Cortex M 3 MCU + RF integration I.C
Lifecycle:
New from this manufacturer.
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