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ADUCRF101BCPZ128R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Data Sheet ADuCRF101
Pin
No. Mnemonic Description
40 P2.4/IRQ8
General-Purpose Input and Output Port 2.4 (P2.4). Do not connect this pin. This pin is
connected internally to the RF transceiver and can be used for debug purposes to
monitor RF transceiver interrupts.
External Interrupt 8 (IRQ8).
41 P0.2/MOSI/PWM0 General-Purpose Input and Output Port 0.2 (P0.2).
SPI1 Master Out, Slave In (MOSI).
PWM Channel 0 (PWM0).
42 P0.1/SCLK General-Purpose Input and Output Port 0.1 (P0.1).
SPI1 Serial Clock (SCLK).
43 P0.0/MISO General-Purpose Input and Output Port 0.0 (P0.0).
SPI1 Master In, Slave Out (MISO).
44 IOVDD General-Purpose I/O Supply
1
. Connect this pin to the battery terminal.
45
P0.7/IRQ3/
CS4/CTS
General-Purpose Input and Output Port 0.7 (P0.7).
External Interrupt 3 (IRQ3).
SPI1 Chip Select 4 (
CS4).
UART Handshake (CTS).
46
BM/P0.6/IRQ2/
CS3/RTS/PWM0 Boot Mode (BM). The ADuCRF101 enters serial download mode if P0.6 is low during, and
for a short time after, an external reset event. It executes user code after any reset event or
if P0.6 is high during an external reset event.
General-Purpose Input and Output Port 0.6 (P0.6).
External Interrupt 2 (IRQ2).
SPI1 Chip Select 3 (
CS3).
UART Handshake (RTS).
PWM Channel 0 (PWM0).
47
RESET
Reset, Active Low. A low signal on this pin for 24 system clocks causes the device to reset.
48
P4.0/PWM0
General-Purpose Input and Output Port 4.0 (P4.0).
PWM Channel 0 (PWM0).
49 P4.1/PWM1 General-Purpose Input and Output Port 4.1 (P4.1).
PWM Channel 1 (PWM1).
50 P4.2/PWM2 General-Purpose Input and Output Port 4.2 (P4.2).
PWM Channel 2 (PWM2).
51 P4.3/PWM3 General-Purpose Input and Output Port 4.3 (P4.3).
PWM Channel 3 (PWM3).
52 P4.4/PWM4 General-Purpose Input and Output Port 4.4 (P4.4).l
PWM Channel 4 (PWM4).
53 P4.5/PWM5 General-Purpose Input and Output Port 4.5 (P4.5).
PWM Channel 5 (PWM5).
54 LFXTAL2 32.768 kHz Watch Crystal Input for Wake-Up Timers.
55 LFXTAL1 32.768 kHz Watch Crystal Output for Wake-Up Timers.
56 VDD_DIG2
Voltage Regulator Output for the Digital Section of the Transceiver. For regulator stability
and noise rejection, place a 220 nF capacitor between this pin and ground.
57 VDDBAT1 Battery Terminal
1
. Supply for the digital section of the transceiver and GPIOs.
58
P4.6/PWM6
General-Purpose Input and Output Port 4.6 (P4.6).
PWM Channel 6 (PWM6).
59 P4.7/PWM7 General-Purpose Input and Output Port 4.7 (P4.7).
PWM Channel 7 (PWM7).
60 ADCVREF
Transceiver ADC Reference Output. For adequate noise rejection, place a 220 nF
capacitor between this pin and ground
61 P3.2/PWMSYNC General-Purpose Input and Output Port 3.2 (P3.2).
PWM Synchronization (PWMSYNC).
62 P3.3/PWMTRIP General-Purpose Input and Output Port 3.3 (P3.3).
PWM Safety Cutoff (PWMTRIP).
Rev. A | Page 15 of 19
ADuCRF101 Data Sheet
Pin
No. Mnemonic Description
63 P3.4 General-Purpose Input and Output Port 3.4.
64 P3.5 General-Purpose Input and Output Port 3.5.
65 EP
Exposed Pad. The exposed package paddle must be soldered to a metal pad on the PCB
and connected to ground.
1
VDDBAT1, VDDBAT2, AVDD, and IOVDD must all be connected together.
2
For detailed information about the DIFF0 to DIFF2 differential input pairs, see theUG-231 User Guide.
3
For detailed information about HFXTAL, a 26 MHz external crystal used to set the RF transceiver communication frequency, see the UG-231 User Guide.
Rev. A | Page 16 of 19
Data Sheet ADuCRF101
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT POWER (dBm)
PA LEVEL MCR
–20
–15
–10
–5
0
5
10
15
0 4 8 12 16 20
24
28 32
36 40
44 48
52
56 60
64
2.2V
3.3V
3.6V
09464-002
Figure 8. Single-Ended PA at 868 MHz, Output Power vs. PA Level
MCR Setting and V
DD
OUTPUT POWER (dBm)
PA LEVEL MCR
–20
–15
–10
–5
0
5
10
15
0 4 8 12 16
20 24 28
32 36 40 44 48 52 56 60 64
–40°C, 2.2V
–40°C, 3.3V
–40°C, 3.6V
+25°C, 2.2V
+25°C, 3.3V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.3V
+85°C, 3.6V
09464-003
Figure 9. Differential PA at 868 MHz; Output Power vs. PA Level MCR Setting,
Temperature, and V
DD
TRANSCEIVER SUPPLY CURRENT (mA)
TRANSCEIVER OUTPUT POWER (dBm)
5
10
15
20
25
30
35
–20 –15 –10 –5
0 5 10 15
09464-004
Figure 10. Single-Ended PA at 868 MHz, Transceiver Supply Current vs.
Transceiver Output Power, V
DD
= 3.3 V
TRANSCEIVER SUPPLY CURRENT (mA)
TRANSCEIVER OUTPUT POWER (dBm)
5
10
15
20
25
30
35
–20 –15 –10 –5 0 5
10 15
09464-005
Figure 11. Differential PA at 868 MHz, Transceiver Supply Current vs.
Transceiver Output Power; V
DD
= 3.3 V
BLOCKING POWER (dBm)
INTERFERER FREQUENCY (MHz)
–10
90
80
70
60
50
40
30
20
10
0
768 788 808 828 848 868 888 908 928 948 968
09464-006
Figure 12. Typical Receiver Wideband Blocking at 868 MHz, V
DD
= 3.3 V,
Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz,
Measured as per ETSI EN 300 220
INTERFERER POWER (dBm)
INTERFERER FREQUENCY (MHz)
–110
–90
–70
–50
–30
–10
10
858 860 862 864
866 868 870 872 874
876 878
09464-007
Figure 13. Typical Receiver Blocking at 868 MHz, V
DD
= 3.3 V,
Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz,
Measured as per ETSI EN 300 220
Rev. A | Page 17 of 19
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ADUCRF101BCPZ128R7

Mfr. #:
Buy ADUCRF101BCPZ128R7
Manufacturer:
Analog Devices Inc.
Description:
RF Microcontrollers - MCU Cortex M 3 MCU + RF integration I.C
Lifecycle:
New from this manufacturer.
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