NCV7710
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11
DETAILED OPERATING AND PIN DESCRIPTION
General
The NCV7710 provides two half−bridge drivers. Strict
adherence to integrated circuit die temperature is necessary,
with a static maximum die temperature of 150°C. Output
drive control and fault reporting are handled via the SPI
(Serial Peripheral Interface) port. A SPI−controlled mode
control provides a low quiescent sleep current mode when
the device is not being utilized. A pull down is provided on
the SI and SCLK inputs to ensure they default to a low state
in the event of a severed input signal. A pull−up is provided
on the CSB input disabling SPI communication in the event
of an open CSB input.
Supply Concept
Power Supply Scheme − VS and VCC
The Vs power supply voltage is used to supply the half
bridges and the high−side drivers. An all−internal
chargepump is implemented to provide the gate−drive
voltage for the n−channel type high−side transistors. The
VCC voltage is used to supply the logic section of the IC,
including the SPI interface.
Due to the independent logic supply voltage the control
and status information will not be lost in case of a loss of Vs
supply voltage. The device is designed to operate inside the
specified parametric limits if the VCC supply voltage is
within the specified voltage range (4.5 V to 5.25 V).
Between the operational level and the VCC undervoltage
threshold level (Vuv_VCC) it is guaranteed that the device
remains in a safe functional state without any inadvertent
change to logic information.
Device / Module Ground Concept
The heat slug is not hard−connected to internal GND rail.
It has to be connected externally.
Power Up/Down Control
In order to prevent uncontrolled operation of the device
during power/up down, an undervoltage lockout feature is
implemented. Both supply voltages (VCC and Vs) are
monitored for undervoltage conditions supporting a safe
power−up transition. When Vs drops below the
undervoltage threshold Vuv_vs(off) (Vs undervoltage
threshold) both output stages are switched to
high−impedance state and the global status bit UOV_OC is
set. This bit is a multi information bit in the Global Status
Byte which is set in case of overcurrent, Vs over− and
undervoltage. In case of undervoltage the status bit
STATUS_2.VSUV is set, too.
Bit CONTROL_3.OVUVR (Vs under−/overvoltage
recovery behavior) can be used to select the desired recovery
behavior after a Vs under−voltage event. In case of OVUVR
= 0, both output stages return to their programmed state as
soon as Vs recovers back to its normal operating range. If
OVUVR is set, the automatic recovery function is disabled
thus the output stages will remain in high−impedance
condition until the status bits have been cleared by the
microcontroller. To avoid high current oscillations in case of
output short to GND and low Vs voltage conditions, it is
recommended to disable the Vs−auto−recovery by setting
OVUVR = 1.
Chargepump
In Standby mode, the chargepump is disabled. After
enabling the device by setting bit CONTROL_0.MODE to
active (1), the internal oscillator is started and the voltage at
the CHP output pin begins to increase. The output drivers are
enabled after a delay of tsact once MODE was set to active.
Driver Outputs
Output PWM Control
For both−half bridge outputs the device features the
possibility to logically combine the SPI−setting with a PWM
signal that can be provided to the inputs PWM1 and
ISOUT/PWM2, respectively. Each of the outputs has a fixed
PWM signal assigned which is shown in Table 1. The PWM
modulation is enabled by the respective bits in the control
registers (CONTROL_2.OUTx_PWMx). In case of using
pin ISOUT/PWM2, the application design has to take care
of either disabling the current sense feature or to provide
sufficient overdrive capability to maintain proper logic input
levels for the PWM input. To improve power performances,
fast PWMing up to 30 kHz is foreseen.
By setting PWM_SWAP bit in the configurations register
CONFIG it is possible to map both outputs to PWM1.
This is useful if PWM control and current sensing is
required at OUT1 and OUT2.
Table 1. PWM CONTROL SCHEME
Output
PWM Control Input
CONFIG.PWM_SWAP = 0 CONFIG.PWM_SWAP = 1
OUT1 PWM1 PWM1
OUT2 PWM2 PWM1
In case of using pin ISOUT/PWM2, the application
design can decide:
• To control all PWM via PWM1 by setting bit
CONFIG.PWM_SWAP to 1
• or to disable the current sense feature
• or to provide sufficient overdrive capability to maintain
proper logic input levels for the PWM input
Due to the used external network connected between
microcontroller and ISOUT/PWM2 pin, the digital input
signal cannot be guaranteed to be a clean digital high or low
level when the current output ISOUT is activated. During
Current sense the PWM2 digital input stays functional (the
input to the digital is not gated), but the internal pull down
on PWM2 is disabled when CS is activated.
