NCV7710DQR2G Datasheet NCV7710DQR2G | P13-P15

NCV7710

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Overvoltage / Undervoltage Shutdown

If the supply voltage Vs rises above the switch off voltage

Vov_vs(off) or falls below Vuv_vs(off), all output

transistors are switched to high−impedance state and the

global status bit UOV_OC (multi information) is set. The

status flag STATUS_2.VSOV, resp. STATUS_2.VSUV is

set, too, to log the over−/under−voltage event. The bit

CONTROL_3.OVUVR can be used to determine the

recovery behavior once the Vs supply voltage gets back into

the specified nominal operating range. OVUVR = 0 enables

auto−recovery, with OVUVR = 1 the output stages remain

in high impedance condition until the status flags have been

cleared. Once set, STATUS2.VSOV / VSUV can only be

reset by a read&clear access to the status register STATUS_2.

Thermal Warning and Overtemperature Shutdown

The device provides a dual−stage overtemperature

protection. If the junction temperature rises above Tjtw_on,

a temperature warning flag (TW) is set in the Global Status

Byte and can be read via SPI. The control software can then

react onto this overload condition by a controlled disable of

individual outputs. If however the junction temperature

reaches the second threshold Tjsd_on, the thermal shutdown

bit TSD is set in the Global Status Byte and all output stages

are switched into high impedance state to protect the device.

The minimum shutdown delay for overtemperature is td_tx.

The output channels can be re−enabled after the device

cooled down and the TSD flag has been reset by the

microcontroller by setting CONTROL_0.MODE = 0.

Openload (Underload) Detection

The openload detection monitors the load current in the

output stage while the transistor is active. If the load current

is below the openload detection threshold for at least td_uld,

the corresponding bit (ULDx) is set in the status registers

STATUS_1. The status of the output remains unchanged.

Once set, ULDx remains set regardless of the actual load

condition. It has to be reset by a read&write access to the

corresponding status register.

Overload Detection

An overcurrent condition is indicated by the flag

(UOV_OC) in the Global Status Byte after a filter time of at

least td_old. The channel dependent overcurrent flags are set

in the status registers (STATUS_0.OCx) and the

corresponding driver is switched into high impedance state

to protect the device. Each low−side and high−side driver

stage provides its own overcurrent flag. Resetting this

overcurrent flag automatically re−enables the respective

output (provided it is still enabled thru the Control register).

If the over current recovery function is enabled, the internal

chip logic automatically resets the overcurrent flag after a

fixed delay time, generating a PWM modulated current with

a programmable duty cycle. Otherwise the status bits have

to be cleared by the microcontroller by a read&clear access

to the corresponding status register.

Cross−current Protection

The half−bridges are protected against cross−currents by

internal circuitry. If one driver is turned off (LS or HS), the

activation of the other driver of the same output will be

automatically delayed by the cross current protection

mechanism until the active driver is safely turned off.

Mode Control

Wake−up and Mode Control

Two different modes are available:

• Active mode

• Standby mode

After power−up of VCC the device starts in Standby

mode. Pulling the chip−select signal CSB to low level causes

the device to change into Active mode (analog part active).

After at least 10 ms delay, the first SPI communication is

valid

and bit CONTROL_0.MODE can be used to set the

desired mode of operation. If bit MODE remains reset (0),

the device returns to the Standby mode after an internal

delay of max. 8

ms, clearing all register content and setting

all output stages into high impedance state.

Standby

Output stages High−Z

Active

Output stages controlled

thru output registers

CSB = 0

MODE = 1

CSB = 0

Delay timer

expired

MODE = 0

and

CSB = 1

Delay (tacts)

Output stages controlled

thru output registers

MODE = 1

Delay (tsact)

CSB = 1

and

MODE = 0

Figure 5. Mode Transitions Diagram

VCC Power−up

Delay (tact)

Output stages Hi−Z

SPI not ready

CSB

SCLK

232221210345

D1 D0D2D19 D18D23 D21D22

active

Mode

CSB = 0

active standby

Mode

CSB = 0

MODE = 0

D20

CONTROL_0.MODE = 1

<8m s

standby

Figure 6. Mode Timing Diagram

NCV7710

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SPI Control

General Description

The 4−wire SPI interface establishes a full duplex

synchronous serial communication link between the

NCV7710 and the application’s microcontroller. The

NCV7710 always operates in slave mode whereas the

controller provides the master function. A SPI access is

performed by applying an active−low slave select signal at

CSB. SI is the data input, SO the data output. The SPI master

provides the clock to the NCV7710 via the SCLK input. The

digital input data is sampled at the rising edge at SCLK. The

data output SO is in high impedance state (tri−state) when

CSB is high. To readout the global error flag without sending

a complete SPI frame, SO indicates the corresponding value

as soon as CSB is set to active. With the first rising edge at

SCLK after the high−to−low transition of CSB, the content

of the selected register is transferred into the output shift

The NCV7710 provides three control registers

(CONTROL_0/2/3), three status registers (STATUS_0/1/2)

and one general configuration register (CONFIG). Each of

these register contains 16−bit data, together with the 8−bit

frame header (access type, register address), the SPI frame

length is therefore 24 bits. In addition to the read/write

accessible registers, the NCV7710 provides five 8−bit ID

registers (ID_HEADER, ID_VERSION, ID_CODE1/2 and

ID_SPI−FRAME) with 8−bit data length. The content of

these registers can still be read out by a 24−bit access, the

data is then transferred in the MSB section of the data frame.

SPI Frame Format

Figure 7 shows the general format of the NCV7710 SPI

frame.

OC1 OC1 A5 A4 A3 A2 A1 A0

DI6 DI2 DI1 DI0

DI7

FLT TF RES TSD TW

UOV

_OC

ULD NRDY DO6 DO2 DO1 DO0DO7 X

CSB

SCLK

Access

Type

Input Data

Device Status Bits Address−dependent Data

Input Data

Figure 7. SPI Frame Format

24−bit SPI Interface

Both 24−bit input and output data are MSB first. Each

SPI−input frame consists of a command byte followed by

two data bytes. The data returned on SO within the same

frame always starts with the global status byte. It provides

general status information about the device. It is then

followed by 2 data bytes (in−frame response) which content

depends on the information transmitted in the command

byte. For write access cycles, the global status byte is

followed by the previous content of the addressed register.

Chip Select Bar (CSB)

CSB is the SPI input pin which controls the data transfer

of the device. When CSB is high, no data transfer is possible

and the output pin SO is set to high impedance. If CSB goes

low, the serial data transfer is allowed and can be started. The

communication ends when CSB goes high again.

Serial Clock (SCLK)

If CSB is set to low, the communication starts with the

rising edge of the SCLK input pin. At each rising edge of

SCLK, the data at the input pin Serial IN (SI) is latched. The

data is shifted out thru the data output pin SO after the falling

edges of SCLK. The clock SCLK must be active only within

the frame time, means when CSB is low. The correct

transmission is monitored by counting the number of clock

pulses during the communication frame. If the number of

SCLK pulses does not correspond to the frame width

indicated in the SPI−frame−ID (Chip ID Register, address

3Eh) the frame will be ignored and the communication

failure bit “TF” in the global status byte will be set. Due to this

safety functionality, daisy chaining the SPI is not possible.

Instead, a parallel operation of the SPI bus by controlling the

CSB signal of the connected ICs is recommended.

Serial Data In (SI)

During the rising edges of SCLK (CSB is low), the data

is transferred into the device thru the input pin SI in a serial

way. The device features a stuck−at−one detection, thus

upon detection of a command = FFFFFFh, the device will be

forced into the Standby mode. All output drivers are

switched off.

NCV7710

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Serial Data Out (SO)

The SO data output driver is activated by a logical low

level at the CSB input and will go from high impedance to

a low or high level depending on the global status bit, FLT

(Global Error Flag). The first rising edge of the SCLK input

after a high to low transition of the CSB pin will transfer the

content of the selected register into the data out shift register.

Each subsequent falling edge of the SCLK will shift the next

bit thru SO out of the device.

Command Byte / Global Status Byte

Each communication frame starts with a command byte

(Table 3). It consists of an operation code (OP[1:0], Table 4)

which specifies the type of operation (Read, Write, Read &

Clear, Readout Device Information) and a six bit address

(A[5:0], Table 5). If less than six address bits are required,

the remaining bits are unused but are reserved. Both Write

and Read mode allow access to the internal registers of the

device. A “Read & Clear”−access is used to read a status

Device Information” allows to read out device related

information such as ID−Header, Product Code, Silicon

Version and Category and the SPI−frame ID. While

receiving the command byte, the global status byte is

transmitted to the microcontroller. It contains global fault

information for the device, as shown in Table 7.

ID Register

Chip ID Information is stored in five special 8−bit ID

registers (Table 6). The content can be read out at the

beginning of the communication.

Table 3. COMMAND BYTE / GLOBAL STATUS BYTE STRUCTURE

Bit

Command Byte (IN) / Global Status Byte (OUT)

23 22 21 20 19 18 17 16

NCV7710 IN OP1 OP0 A5 A4 A3 A2 A1 A0

NCV7710 OUT FLT TF RESB TSD TW UOV_OC ULD NRDY

Reset Value 1 0 0 0 0 0 0 1

Table 4. COMMAND BYTE, ACCESS MODE

OP1 OP0 Description

0 0 Write Access (W)

0 1 Read Access ( R)

1 0 Read and Clear Access (RC)

1 1 Read Device ID (RDID)

Table 5. COMMAND BYTE, REGISTER ADDRESS

A[5:0] Access Description Content

00h R/W

Control Register

CONTROL_0

Device mode control, Bridge outputs control

02h R/W

Control Register

CONTROL_2

Bridge outputs recovery control, PWM enable

03h R/W

Control Register

CONTROL_3

Current Sense selection

10h R/RC

Status Register

STATUS_0

Bridge outputs Overcurrent diagnosis

11h R/RC

Status Register

STATUS_1

Bridge outputs Underload diagnosis

12h R/RC

Status Register

STATUS_2

Vs Over− and Undervoltage

3Fh R/W

Configuration Register

CONFIG

Mask bits for global fault bits, PWM mapping

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

NCV7710DQR2G

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Motor / Motion / Ignition Controllers & Drivers DOOR LOCK DVR IC LIGHT

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