NCV7710
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19
STATUS_1 Register
Address: 11h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − − − − − R/RC R/RC R/RC R/RC − − − − − −
Bit name 0 0 0 0 0 0
ULD
HS1
ULD
LS1
ULD
HS2
ULD
LS2
0 0 0 0 0 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Underload
Detection
ULDx Description Remark
0 No underload detected
For each output stage an underload status bit ULD is available. The underload
detection is done in “on−mode”. If the load current is below the undercurrent
detection threshold for at least td_uld , the corresponding underload bit ULDx is
set.
If an ULD event occurs the global status bit ULD will be set. With setting
CONFIG.NO_ULD_OUTn the global ULD failure bit is deactivated in general.
1 Underload detected
STATUS_2 Register
Address: 12h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − − − − − − − − − − − R/RC R/RC − −
Bit name 0 0 0 0 0 0 0 0 0 0 0 0 VSUV VSOV 0 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Vs Undervoltage
VSUV Description Remark
0 No undervoltage detected
In case of an Vs undervoltage event, the output stages will be deactivated
immediately and the corresponding failure flag will be set. By default the
output stages will be reactivated automatically after Vs is recovered unless
the control bit CONTROL_3.OVUVR is set. If this is the case (OVUVR=1)
the bit VSUV has to be cleared after an UV event.
1 Undervoltage detected
Vs Overvoltage
VSOV Description Remark
0 No overvoltage detected
In case of an Vs overvoltage event, the output stages will be deactivated
immediately and the corresponding failure flag will be set. By default the
output stages will be reactivated automatically after Vs is recovered unless
the control bit CONTROL_3.OVUVR is set. If this is the case (OVUVR=1)
the bit VSOV has to be cleared after an OV event.
1 Overvoltage detected
