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NCV7710DQR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
NCV7710
www.onsemi.com
16
Table 6. CHIP ID INFORMATION
A[5:0] Access Description Content
00h RDID ID header 4300h
01h RDID Version 0000h
02h RDID Product Code 1 7700h
03h RDID Product Code 2 0A00h
3Eh RDID SPI−Frame ID 0200h
Table 7. GLOBAL STATUS BYTE CONTENT
FLT Global Fault Bit
0 No fault Condition
Failures of the Global Status Byte, bits [6:0] are always linked to the Global Fault Bit FLT. This bit
is generated by an OR combination of all failure bits of the device (RESB inverted). It is reflected
via the SO pin while CSB is held low and NO clock signal is present (before first positive edge of
SCLK). The flag will remain valid as long as CSB is held low. This operation does not cause the
Transmission error Flag in the Global Status Byte to be set. Signals TW and ULD can be masked.
1 Fault Condition
TF SPI Transmission Error
0 No Error
If the number of clock pulses within the previous frame was unequal 0 (FLT polling) or 24. The
frame was ignored and this flag was set.
1 Error
RESB Reset Bar (Active low)
0 Reset
Bit is set to “0” after a Power−on−Reset or a stuck−at−1 fault at SI (SPI−input data = FFFFFFh)
has been detected. All outputs are disabled.
1 Normal Operation
TSD Overtemperature Shutdown
0 No Thermal Shutdown
Thermal Shutdown Status indication. In case of a Thermal Shutdown, all output drivers including
the charge pump output are deactivated (high impedance). The TSD bit has to be cleared thru a
SW reset to reactivate the output drivers and the chargepump output.
1 Thermal Shutdown
TW Thermal Warning
0 No Thermal Warning
This bit indicates a pre−warning level of the junction temperature. It is maskable by the
Configuration Register (CONFIG.NO_TW).
1 Thermal Warning
UOV_OC VS Monitoring, Overcurrent Status
0 No Fault
This bit represents a logical OR combination of under−/overvoltage signals (VS) and overcurrent
signals.
1 Fault
ULD Underload
0 No Underload
This bit represents a logical OR combination of all underload signals. It is maskable by the
Configuration Register (CONFIG.NO_ULDx).
1 Underload
NRDY Not Ready
0 Device Ready
After transition from Standby to Active mode, an internal timer is started to allow the internal
chargepump to settle before any outputs can be activated. This bit is cleared automatically after
the startup is completed.
1 Device Not Ready
NCV7710
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17
SPI REGISTERS CONTENT
CONTROL_0 Register
Address: 00h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − − − − − RW RW RW RW − − − − − RW
Bit name 0 0 0 0 0 0 HS1 LS1 HS2 LS2 0 0 0 0 0 MODE
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HS/LS
Outputs
Control
HSx LSx Description Remark
0 0 default OUTx High impedance
If a driver is enabled by the control register AND the
corresponding PWM enable bit is set in CONTROL_2
register, the HS output is activated if PWM1 (PWM2)
input signal is high, LS is activated otherwise.
Since OUT1 and OUT2 are half−bridge outputs,
activating both HS and LS at the same time is prevented
by internal logic.
0 1 LSx enabled
1 0 HSx enabled
1 1
OUTx High impedance /
LS or HS enabled in PWM
Mode
Control
MODE Description Remark
0 default Standby
If MODE is set, the device is switched to Active mode.
Resetting MODE forces the device to transition into
Standby mode, all internal memory is cleared, all output
stages are switched into their default state (off).
1 Active
CONTROL_2 Register
Address: 02h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − − RW RW − − − − − − RW RW − − −
Bit name 0 0 0 OCR1 OCR2 0 0 0 0 0 0
OUT1
PWM1
OUT2
PWM2
0 0 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overcurrent
Recovery
OCRx Description Remark
0 default
Overcurrent Recovery
disabled
During an overcurrent event the overcurrent status bit
STATUS_0.OCx is set and the dedicated output is
switched off. (The global multi bit UOV_OC is set, also).
When the overcurrent recovery bit is enabled, the output
will be reactivated automatically after a programmable
delay time (CONTROL_3.OCRF).
1
Overcurrent Recovery
enabled
PWM1/2
Selection
OUTx PWM Description Remark
0 default PWMx not selected
For the outputs it is possible to select the PWM input
pins PWM1 or PWM2. In this case the dedicated output
(selected in CONTROL_0 register) is on if the PWM input
signal is high. By default, OUT2 is controlled by PWM2,
OUT1 is controlled by PWM1. By setting
CONFIG.PWM_SWAP bit, both outputs are mapped to
PWM1
1 PWMx selected
NCV7710
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18
CONTROL_3 Register
Address: 03h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − − − − − − − − − RW RW − RW RW RW
Bit name 0 0 0 0 0 0 0 0 0 0 OCRF OVUVR 0 IS2 IS1 IS0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overcurrent
Recovery
Frequency
Selection
OCRF Description Remark
0 default
Slow Overcurrent recovery
mode
If the overcurrent recovery bit is set, the output will be
switched on automatically after a delay time.
1
Fast Overcurrent recovery
mode
Over−/Under−
voltage
Recovery
OVUVR Description Remark
0 default
Over− and undervoltage
recovery function enabled
If the OV/UV recovery is disabled by setting
OVUVR=1, the status register STATUS_2 bits VSOV
or VSUV have to be cleared after an OV/UV event to
reactivate the outputs.
1
No over− and undervoltage
recovery
Current
Sensing
Selection
IS2 IS1 IS0 Description Remark
0 0 0 current sensing deactivated
The current in high−side power stages can be
monitored at the bidirectional multifunctional pin
ISOUT/PWM2.
This pin is a multifunctional pin and can be activated
as output by setting the current selection bits IS[2:0].
The selected high−side output will be multiplexed to
the output ISOUT.
0 0 1 current sensing deactivated
0 1 0 current sensing deactivated
0 1 1 OUT1
1 0 0 OUT2
1 0 1 current sensing deactivated
1 1 0 current sensing deactivated
1 1 1 current sensing deactivated
STATUS_0 Register
Address: 10h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Access type − − − − − − R/RC R/RC R/RC R/RC − − − − − −
Bit name 0 0 0 0 0 0
OC
HS1
OC
LS1
OC
HS2
OC
LS2
0 0 0 0 0 0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Overcurrent
Detection
OCx Description Remark
0 No overcurrent detected
During an overcurrent event in one of the HS or LS, the belonging overcurrent
status bit STATUS_0.OCx is set and the dedicated output is switched off. (The
global multi bit UOV_OC is set, also). When the overcurrent recovery bit is
enabled, the output will be reactivated automatically after a programmable
delay time (CONTROL_3.OCRF). If the overcurrent recovery bit is not set the
microcontroller has to clear the OC failure bit and to reactivate the output stage
again.
1 Overcurrent detected
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

NCV7710DQR2G

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Buy NCV7710DQR2G
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers DOOR LOCK DVR IC LIGHT
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