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MT41J256M16LY-091G:N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Table 10: gDDR3-2200 Speed Bins
gDDR3-2200 Speed Bin -091G
Unit Notes
CL-
t
RCD-
t
RP 15-15-15
Parameter Symbol Min Max
ACTIVATE to internal READ or WRITE delay time
t
RCD 13.65 – ns
PRECHARGE command period
t
RP 13.65 – ns
ACTIVATE-to-ACTIVATE or REFRESH command period
t
RC 46.13 – ns
ACTIVATE-to-PRECHARGE command period
t
RAS 33 9 x
t
REFI ns 1
CL = 5 CWL = 5
t
CK (AVG) 3.0 3.3 ns 2
CWL = 6, 7, 8, 9
t
CK (AVG) Reserved ns 3
CL = 6 CWL = 5
t
CK (AVG) 2.5 3.3 ns 2
CWL = 6, 7, 8, 9
t
CK (AVG) Reserved ns 3
CL = 7 CWL = 5, 7, 8, 9
t
CK (AVG) 2.5 3.3 ns 2
CWL = 6
t
CK (AVG) Reserved ns 3
CL = 8 CWL = 5, 7, 8, 9
t
CK (AVG) Reserved ns 3
CWL = 6
t
CK (AVG) 1.875 <2.5 ns 2
CL = 9 CWL = 5, 6, 8, 9
t
CK (AVG) Reserved ns 3
CWL = 7
t
CK (AVG) 1.875 <2.5 ns 2
CL = 10 CWL = 5, 6, 9
t
CK (AVG) Reserved ns 3
CWL = 7
t
CK (AVG) 1.5 <1.875 ns 2
CWL = 8
t
CK (AVG) Reserved ns 3
CL = 11 CWL = 5, 6, 7
t
CK (AVG) Reserved ns 3
CWL = 8
t
CK (AVG) 1.5 <1.875 ns 2
CWL = 9
t
CK (AVG) Reserved ns 3
CL - 12 CWL = 5, 6, 7, 8
t
CK (AVG) Reserved ns 3
CWL = 9
t
CK (AVG) Reserved ns 3
CL = 13 CWL = 5, 6, 7, 8
t
CK (AVG) Reserved ns 3
CWL = 9
t
CK (AVG) 1.1 <1.25 ns 2
CL = 14 CWL = 5, 6, 7, 8, 9
t
CK (AVG) 1 <1.1 ns 2
CWL = 10
CL=15 CWL = 5, 6, 7, 8, 9, 10
t
CK (AVG) .091 <1 ns 2
CWL = 11
Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13, 14,
15
CK
Supported CWL settings 5, 6, 7, 8, 9, 10, 11 CK
Notes:
1.
t
REFI depends on T
OPER
.
2. The CL and CWL settings result in
t
CK requirements. When making a selection of
t
CK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Speed Bin Tables
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Electrical Characteristics and AC Operating Conditions
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-2000 gDDR3-2200
Unit NotesMin Max Min Max
Clock Timing
Clock period average:
DLL disable mode
T
C
= 0°C to 85°C
t
CK (DLL_DIS) 8 7800 8 7800 ns 9, 42
T
C
= >85°C to 115°C 8 3900 8 3900 ns 42
Clock period average: DLL enable mode
t
CK (AVG) See corresponding speed bin table for
t
CK
range allowed
ns 10, 11
High pulse width average
t
CH (AVG) 0.47 0.53 0.47 0.53 CK 12
Low pulse width average
t
CL (AVG) 0.47 0.53 0.47 0.53 CK 12
Clock period jitter DLL locked
t
JIT
PER
–60 60 –60 60 ps 13
DLL locking
t
JIT
PER
,lck –50 50 –50 50 ps 13
Clock absolute period
t
CK (ABS) MIN =
t
CK (AVG) MIN +
t
JIT
PER
MIN;
MAX =
t
CK (AVG) MAX +
t
JIT
PER
MAX
ps
Clock absolute high pulse width
t
CH (ABS) 0.43 – 0.43 –
t
CK
(AVG)
14
Clock absolute low pulse width
t
CL (ABS) 0.43 – 0.43 –
t
CK
(AVG)
15
Cycle-to-cycle jitter DLL locked
t
JIT
CC
120 120 ps 16
DLL locking
t
JIT
CC
,lck 100 100 ps 16
Cumulative error across 2 cycles
t
ERR2
PER
–88 88 –88 88 ps 17
3 cycles
t
ERR3
PER
–105 105 –105 105 ps 17
4 cycles
t
ERR4
PER
–117 117 –117 117 ps 17
5 cycles
t
ERR5
PER
–126 126 –126 126 ps 17
6 cycles
t
ERR6
PER
–133 133 –133 133 ps 17
7 cycles
t
ERR7
PER
–139 139 –139 139 ps 17
8 cycles
t
ERR8
PER
–145 145 –145 145 ps 17
9 cycles
t
ERR9
PER
–150 150 –150 150 ps 17
10 cycles
t
ERR10
PER
–154 154 –154 154 ps 17
11 cycles
t
ERR11
PER
–158 158 –158 158 ps 17
12 cycles
t
ERR12
PER
–161 161 –161 161 ps 17
n = 13, 14 . . .49, 50
cycles
t
ERRnper
t
ERRn
PER
MIN = (1 + 0.68in[n]) ×
t
JIT
PER
MIN
t
ERRn
PER
MAX = (1 + 0.68in[n]) ×
t
JIT
PER
MAX
ps 17
DQ Input Timing
Data setup time to DQS,
DQS#
Base (specification)
t
DS
(AC175)
– – – – ps 18, 19
V
REF
@ 1 V/ns – – – – ps 19, 20
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-2000 gDDR3-2200
Unit NotesMin Max Min Max
Data setup time to DQS,
DQS#
Base (specification)
t
DS
(AC150)
– – 10 – ps 18, 19
V
REF
@ 1 V/ns – – 160 – ps 19, 20
Data setup time to DQS,
DQS#
Base (specification)@
2 V/ns
t
DS
(AC135)
68 – – – ps 19, 20
V
REF
@ 2 V/ns 135 – – – 19, 20
Data hold time from
DQS, DQS#
Base (specification)
t
DH
(DC100)
70 – 70 – ps 18, 19
V
REF
@ 1 V/ns 120 – 120 – ps 19, 20
Minimum data pulse width
t
DIPW 320 – 320 – ps 41
DQ Output Timing
DQS, DQS# to DQ skew, per access
t
DQSQ – 85 – 85 ps
DQ output hold time from DQS, DQS#
t
QH 0.38 – 0.38 –
t
CK
(AVG)
21
DQ Low-Z time from CK, CK#
t
LZ (DQ) –390 195 –390 195 ps 22, 23
DQ High-Z time from CK, CK#
t
HZ (DQ) – 195 – 195 ps 22, 23
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising
t
DQSS –0.27 0.27 –0.27 0.27 CK 25
DQS, DQS# differential input low pulse width
t
DQSL 0.45 0.55 0.45 0.55 CK
DQS, DQS# differential input high pulse width
t
DQSH 0.45 0.55 0.45 0.55 CK
DQS, DQS# falling setup to CK, CK# rising
t
DSS 0.18 – 0.18 – CK 25
DQS, DQS# falling hold from CK, CK# rising
t
DSH 0.18 – 0.18 – CK 25
DQS, DQS# differential WRITE preamble
t
WPRE 0.9 – 0.9 – CK
DQS, DQS# differential WRITE postamble
t
WPST 0.3 – 0.3 – CK
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
t
DQSCK –195 195 –195 195 ps 23
DQS, DQS# rising to/from rising CK, CK# when
DLL is disabled
t
DQSCK
(DLL_DIS)
1 10 1 10 ns 26
DQS, DQS# differential output high time
t
QSH 0.40 – 0.40 – CK 21
DQS, DQS# differential output low time
t
QSL 0.40 – 0.40 – CK 21
DQS, DQS# Low-Z time (RL - 1)
t
LZ (DQS) –390 195 –391 195 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2)
t
HZ (DQS) – 195 – 195 ps 22, 23
DQS, DQS# differential READ preamble
t
RPRE 0.9 Note 24 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble
t
RPST 0.3 Note 27 0.3 Note 27 CK 23, 27
Command and Address Timing
DLL locking time
t
DLLK 512 – 512 – CK 28
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC175)
– – 45 – ps 29, 30
V
REF
@ 1 V/ns – – 220 – ps 20, 30
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

MT41J256M16LY-091G:N

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IC DRAM 4G PARALLEL 1GHZ 96FBGA
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