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MT41J256M16LY-091G:N

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Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-2000 gDDR3-2200
Unit NotesMin Max Min Max
Write leveling setup from rising CK, CK# cross-
ing to rising DQS, DQS# crossing
t
WLS 140 – 140 – ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
t
WLH 140 – 140 – ps
Write leveling output delay
t
WLO 0 7.5 0 7.5 ns
Write leveling output error
t
WLOE 0 2 0 2 ns
Parameter Symbol
gDDR3-1600 gDDR3-1800
Unit NotesMin Max Min Max
Clock Timing
Clock period average:
DLL disable mode
T
C
= 0°C to 85°C
t
CK (DLL_DIS) 8 7800 8 7800 ns 9, 42
T
C
= >85°C to 115°C 8 3900 8 3900 ns 42
Clock period average: DLL enable mode
t
CK (AVG) See corresponding speed bin table for
t
CK
range allowed
ns 10, 11
High pulse width average
t
CH (AVG) 0.47 0.53 0.47 0.53 CK 12
Low pulse width average
t
CL (AVG) 0.47 0.53 0.47 0.53 CK 12
Clock period jitter DLL locked
t
JIT
PER
–80 80 –70 70 ps 13
DLL locking
t
JIT
PER
,lck –70 70 –60 60 ps 13
Clock absolute period
t
CK (ABS) MIN =
t
CK (AVG) MIN +
t
JIT
PER
MIN;
MAX =
t
CK (AVG) MAX +
t
JIT
PER
MAX
ps
Clock absolute high pulse width
t
CH (ABS) 0.43 – 0.43 –
t
CK
(AVG)
14
Clock absolute low pulse width
t
CL (ABS) 0.43 – 0.43 –
t
CK
(AVG)
15
Cycle-to-cycle jitter DLL locked
t
JIT
CC
160 140 ps 16
DLL locking
t
JIT
CC
,lck 140 120 ps 16
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-1600 gDDR3-1800
Unit NotesMin Max Min Max
Cumulative error across 2 cycles
t
ERR2
PER
–118 118 –103 103 ps 17
3 cycles
t
ERR3
PER
–140 140 –122 122 ps 17
4 cycles
t
ERR4
PER
–155 155 –136 136 ps 17
5 cycles
t
ERR5
PER
–168 168 –147 147 ps 17
6 cycles
t
ERR6
PER
–177 177 –155 155 ps 17
7 cycles
t
ERR7
PER
–186 186 –163 163 ps 17
8 cycles
t
ERR8
PER
–193 193 –169 169 ps 17
9 cycles
t
ERR9
PER
–200 200 –175 175 ps 17
10 cycles
t
ERR10
PER
–205 205 –180 180 ps 17
11 cycles
t
ERR11
PER
–210 210 –184 184 ps 17
12 cycles
t
ERR12
PER
–215 215 –188 188 ps 17
n = 13, 14 . . .49, 50
cycles
t
ERRnper
t
ERRn
PER
MIN = (1 + 0.68in[n]) ×
t
JIT
PER
MIN
t
ERRn
PER
MAX = (1 + 0.68in[n]) ×
t
JIT
PER
MAX
ps 17
DQ Input Timing
Data setup time to DQS,
DQS#
Base (specification)
t
DS
(AC175)
– – – – ps 18, 19
V
REF
@ 1 V/ns – – – – ps 19, 20
Data setup time to DQS,
DQS#
Base (specification)
t
DS
(AC150)
30 – 10 – ps 18, 19
V
REF
@ 1 V/ns 180 – 160 – ps 19, 20
Data setup time to DQS,
DQS#
Base (specification)@
2 V/ns
t
DS
(AC135)
– – – – ps 19, 20
V
REF
@ 2 V/ns – – – – 19, 20
Data hold time from
DQS, DQS#
Base (specification)
t
DH
(DC100)
65 – 45 – ps 18, 19
V
REF
@ 1 V/ns 165 – 145 – ps 19, 20
Minimum data pulse width
t
DIPW 400 – 360 – ps 41
DQ Output Timing
DQS, DQS# to DQ skew, per access
t
DQSQ – 125 – 100 ps
DQ output hold time from DQS, DQS#
t
QH 0.38 – 0.38 –
t
CK
(AVG)
21
DQ Low-Z time from CK, CK#
t
LZ (DQ) –500 250 –450 225 ps 22, 23
DQ High-Z time from CK, CK#
t
HZ (DQ) – 250 – 225 ps 22, 23
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising
t
DQSS –0.25 0.25 –0.27 0.27 CK 25
DQS, DQS# differential input low pulse width
t
DQSL 0.45 0.55 0.45 0.55 CK
DQS, DQS# differential input high pulse width
t
DQSH 0.45 0.55 0.45 0.55 CK
DQS, DQS# falling setup to CK, CK# rising
t
DSS 0.2 – 0.18 – CK 25
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-1600 gDDR3-1800
Unit NotesMin Max Min Max
DQS, DQS# falling hold from CK, CK# rising
t
DSH 0.2 – 0.18 – CK 25
DQS, DQS# differential WRITE preamble
t
WPRE 0.9 – 0.9 – CK
DQS, DQS# differential WRITE postamble
t
WPST 0.3 – 0.3 – CK
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
t
DQSCK –255 255 –225 225 ps 23
DQS, DQS# rising to/from rising CK, CK# when
DLL is disabled
t
DQSCK
(DLL_DIS)
1 10 1 10 ns 26
DQS, DQS# differential output high time
t
QSH 0.40 – 0.40 – CK 21
DQS, DQS# differential output low time
t
QSL 0.40 – 0.40 – CK 21
DQS, DQS# Low-Z time (RL - 1)
t
LZ (DQS) –500 250 –450 225 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2)
t
HZ (DQS) – 250 – 225 ps 22, 23
DQS, DQS# differential READ preamble
t
RPRE 0.9 Note 24 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble
t
RPST 0.3 Note 27 0.3 Note 27 CK 23, 27
Command and Address Timing
DLL locking time
t
DLLK 512 – 512 – CK 28
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC175)
65 – 45 – ps 29, 30
V
REF
@ 1 V/ns 240 – 220 – ps 20, 30
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC150)
190 – 170 – ps 29, 30
V
REF
@ 1 V/ns 340 – 320 – ps 20, 30
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC135)
– – – – ps
V
REF
@ 1 V/ns – – – – ps
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC125)
– – – – ps
V
REF
@ 1 V/ns – – – – ps
CTRL, CMD, ADDR hold
from CK,CK#
Base (specification)
t
IH
(DC100)
140 – 120 – ps 29, 30
V
REF
@ 1 V/ns 240 – 220 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width
t
IPW 620 – 560 – ps 41
ACTIVATE to internal READ or WRITE delay
t
RCD See corresponding speed bin table for
t
RCD
ns 31
PRECHARGE command period
t
RP See corresponding speed bin table for
t
RP
ns 31
ACTIVATE-to-PRECHARGE command period
t
RAS See corresponding speed bin table for
t
RAS
ns 31, 32
ACTIVATE-to-ACTIVATE command period
t
RC See corresponding speed bin table for
t
RC
ns 31
ACTIVATE-to-ACTIVATE
minimum command period
t
RRD MIN = greater of
4CK or 7.5ns
MIN = greater of
4CK or 7.5ns
CK 31
Four ACTIVATE
windows
t
FAW 45 – 40 – ns 31
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

MT41J256M16LY-091G:N

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Buy MT41J256M16LY-091G:N
Manufacturer:
Micron
Description:
IC DRAM 4G PARALLEL 1GHZ 96FBGA
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